A–19

A.5.1.3 USB Interrupt Mask Register (USBMSK – Address FFFDh)

The USB interrupt mask register contains the interrupt mask bits used to enable or disable the generation of interrupts

based on the corresponding status bits.

Bit 7 6 5 4 3 2 1 0

Mnemonic RSTR SUSR RESR SOF PSOF SETUP — STPOW

Type R/W R/W R/W R/W R/W R/W R R/W

Default 0 0 0 0 0 0 0 0

BIT MNEMONIC NAME DESCRIPTION

7 RSTR Function reset The function reset interrupt mask bit is set to a 1 by the MCU to enable the USB

function reset interrupt.

6 SUSR Function suspend The function suspend interrupt mask bit is set to a 1 by the MCU to enable the USB

function suspend interrupt.

5 RESR Function resume The function resume interrupt mask bit is set to a 1 by the MCU to enable the USB

function resume interrupt.

4 SOF Start-of-frame The start-of-frame interrupt mask bit is set to a 1 by the MCU to enable the USB

start-of-frame interrupt.

3 PSOF Pseudo start-of-frame The pseudo start-of-frame interrupt mask bit is set to a 1 by the MCU to enable the

USB pseudo start-of-frame interrupt.

2 SETUP Setup stage transaction The setup stage transaction interrupt mask bit is set to a 1 by the MCU to enable the

USB setup stage transaction interrupt.

1 — Reserved Reserved for future use

0 STPOW Setup stage transaction over-

write

The setup stage transaction over-write interrupt mask bit is set to a 1 by the MCU to

enable the USB setup stage transaction over-write interrupt.

A.5.1.4 USB Control Register (USBCTL – Address FFFCh)

The USB control register contains various control bits used for USB operations.

Bit 7 6 5 4 3 2 1 0

Mnemonic CONT FEN RWUP FRSTE — — — —

Type R/W R/W R/W R/W R R R R

Default 0 0 0 0 0 0 0 0

BIT MNEMONIC NAME DESCRIPTION

7 CONT Function connect The function connect bit is set to a 1 by the MCU to connect the TUSB3200 device to

the USB. As a result of connecting to the USB, the host PC should enumerate the

function. When this bit is set, the USB data plus pullup resistor (PUR) output signal is

enabled, which will connect the pullup on the PCB to the TUSB3200 3.3-V supply

voltage. When this bit is cleared to a 0, the PUR output is in the 3-state mode. This bit

is not affected by a USB reset.

6 FEN Function enable The function enable bit is set to a 1 by the MCU to enable the TUSB3200 device to

respond to USB transactions. If this bit is cleared to a 0, the UBM will ignore all USB

transactions. This bit is cleared by a USB reset.

5 RWUP Remote wake-up The remote wake-up bit is set to a 1 by the MCU to request the suspend/resume

logic to generate resume signaling upstream on the USB. This bit is used to exit a

USB low-power suspend state when a remote wake-up event occurs. After initiating

the resume signaling by setting this bit, the MCU should clear this bit within 2.5 µs.

4 FRSTE Function reset enable The function reset enable bit is set to a 1 by the MCU to enable the USB reset to reset

all internal logic including the MCU. However, the shadow the ROM (SDW) and the

USB function connect (CONT) bits will not be reset. When this bit is set, the reset

output (RSTO

) signal from the TUSB3200 device will also be active when a USB

reset occurs. This bit is not affected by USB reset.

3:0 — Reserved Reserved for future use

A–20

A.5.1.5 USB Frame Number Register (Low Byte) (USBFNL – Address FFFBh)

The USB frame number register (low byte) contains the least significant byte of the 11-bit frame number value

received from the host PC in the start-of-frame packet.

Bit 7 6 5 4 3 2 1 0

Mnemonic FN7 FN6 FN5 FN4 FN3 FN2 FN1 FN0

Type R R R R R R R R

Default 0 0 0 0 0 0 0 0

BIT MNEMONIC NAME DESCRIPTION

7:0 FN(7:0) Frame number The frame number bit values are updated by hardware each USB frame with the

frame number field value received in the USB start-of-frame packet. The frame

number can be used as a time stamp by the USB function. If the TUSB3200 frame

timer is not locked to the host PC frame timer, then the frame number is incremented

from the previous value when a pseudo start-of-frame occurs.

A.5.1.6 USB Frame Number Register (High Byte) (USBFNH – Address FFFAh)

The USB frame number register (high byte) contains the most significant 3 bits of the 11-bit frame number value

received from the host PC in the start-of-frame packet.

Bit 7 6 5 4 3 2 1 0

Mnemonic — — — — — FN10 FN9 FN8

Type R R R R R R R R

Default 0 0 0 0 0 0 0 0

BIT MNEMONIC NAME DESCRIPTION

7:3 — Reserved Reserved for future use.

2:0 FN(10:8) Frame number The frame number bit values are updated by hardware each USB frame with the

frame number field value received in the USB start-of-frame packet. The frame

number can be used as a time stamp by the USB function. If the TUSB3200 frame

timer is not locked to the host PC frame timer, then the frame number is incremented

from the previous value when a pseudo start-of-frame occurs.

A.5.2 DMA Registers

This section describes the memory-mapped registers used for the four DMA channels. Each DMA channel has a set

of three registers.

A.5.2.1 DMA Channel 3 Time Slot Assignment Register (Low Byte) (DMATSL3 – Address FFF9h)

The DMA channel 3 time slot assignment register (low byte) contains the eight least significant time slot bits. The time

slot assignment bits are used to define which CODEC port interface time slots are supported by DMA channel 3. The

DMA channel will control the transfer of data between the USB endpoint buffers and the CODEC port interface

registers based on which bits are set. The direction of the data transfer depends on the value of the USB endpoint

direction bit (EPDIR) in the DMA channel 3 control register. The desired time slot bits should be set by the MCU before

the DMA channel is enabled. There are a total of fourteen time slot bits for each DMA channel.

Bit 7 6 5 4 3 2 1 0

Mnemonic TSL7 TSL6 TSL5 TSL4 TSL3 TSL2 TSL1 TSL0

Type R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0

BIT MNEMONIC NAME DESCRIPTION

7:0 TSL(7:0) Time slot assignment The DMA time slot assignment bits are set to a 1 by the MCU to define the CODEC

port interface time slots supported by this DMA channel.

A–21

A.5.2.2 DMA Channel 3 Time Slot Assignment Register (High Byte) (DMATSH3 – Address FFF8h)

The DMA channel 3 time slot assignment register (high byte) contains the six most significant time slot bits. In addition,

this register contains the bytes per time slot control bits.

Bit 7 6 5 4 3 2 1 0

Mnemonic BPTS1 BPTS0 TSL13 TSL12 TSL11 TSL10 TSL9 TSL8

Type R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0

BIT MNEMONIC NAME DESCRIPTION

7:6 BPTS(1:0) Bytes per time slot The bytes per time slot bits are used to define the number of bytes to be transferred

for each time slot supported by this DMA channel.

00b = 1 byte, 01b = 2 bytes, 10b = 3 bytes, 11b = 4 bytes

5:0 TSL(13:8) Time slot assignment The DMA time slot assignment bits are set to a 1 by the MCU to define the CODEC

port interface time slots supported by this DMA channel.

A.5.2.3 DMA Channel 3 Control Register (DMACTL3 – Address FFF7h)

The DMA channel 3 control register is used to store various control bits for DMA channel 3.

Bit 7 6 5 4 3 2 1 0

Mnemonic DMAEN WABEN — — EPDIR EPNUM2 EPNUM1 EPNUM0

Type R/W R/W R R R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0

BIT MNEMONIC NAME DESCRIPTION

7 DMAEN DMA enable The DMA enable bit is set to a 1 by the MCU to enable this DMA channel. Before

enabling the DMA channel, all other DMA channel configuration bits should be set to

the desired value.

6 WABEN Wrap-around buffer enable The wrap-around buffer enable bit is used by the MCU to enable or disable the

wrap-around buffer operation. The wrap-around buffer operation can only be used

by isochronous out endpoints or isochronous in endpoints that are serviced by the

DMA channels. The wrap-around buffer operation is enabled or disabled separately

for each DMA channel. For a DMA channel, the MCU should set this bit to a 1 to

enable the wrap-around buffer operation and clear this bit to a 0 to disable the

wrap-around buffer operation. Both the DMA channel and UBM logic use this bit to

determine the required functionality.

5 — Reserved Reserved for future use

4 — Reserved Reserved for future use

3 EPDIR USB endpoint direction The USB endpoint direction bit controls the direction of data transfer by this DMA

channel. The MCU should set this bit to a 1 to configure this DMA channel to be used

for a USB in endpoint. The MCU should clear this bit to a 0 to configure this DMA

channel to be used for a USB out endpoint.

2:0 EPNUM(2:0) USB endpoint number The USB endpoint number bits are set by the MCU to define the USB endpoint

number supported by this DMA channel. Keep in mind that endpoint 0 is always

used for the control endpoint, which is serviced by the MCU and not a DMA channel.

001b = Endpoint 1, 010b = Endpoint 2, …, 111b = Endpoint 7

Part #	TUSB3200ACPAH
Description	USB STREAMING CONTROLLER
Category	IC
Availability	Out of Stock
Qty	0

TUSB3200ACPAH

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Technical Document