A–13
A.4.4.5 USB In Endpoint – X Buffer Base Address Byte (IEPBBAXx)
The USB in endpoint X buffer base address byte contains the 8-bit value used to specify the base memory location
for the X data buffer for a particular USB in endpoint.
Bit 7 6 5 4 3 2 1 0
Mnemonic BBAX10 BBAX9 BBAX8 BBAX7 BBAX6 BBAX5 BBAX4 BBAX3
Type R/W R/W R/W R/W R/W R/W R/W R/W
BIT MNEMONIC NAME DESCRIPTION
7:0 BBAX(10:3) X Buffer base address The X buffer base address value is set by the MCU to program the base address
location in memory to be used for the X data buffer. A total of 11 bits is used to specify
the base address location. This byte specifies the most significant 8 bits of the
address. All 0s are used by the hardware for the three least significant bits.
A.4.4.6 USB In Endpoint – Configuration Byte (IEPCNFx)
The USB in endpoint configuration byte contains the various bits used to configure and control the endpoint. Note
that the bits in this byte take on different functionality based on the type of endpoint defined. Basically, the control,
interrupt and bulk endpoints function differently than the isochronous endpoints.
A.4.4.6.1 USB In Endpoint – Control, Interrupt or Bulk Configuration Byte
This section defines the functionality of the bits in the USB in endpoint configuration byte for control, interrupt, and
bulk endpoints.
Bit 7 6 5 4 3 2 1 0
Mnemonic IEPEN ISO TOGGLE DBUF STALL IEPIE — —
Type R/W R/W R/W R/W R/W R/W R/W R/W
BIT MNEMONIC NAME DESCRIPTION
7 IEPEN Endpoint enable The endpoint enable bit is set to a 1 by the MCU to enable the in endpoint. This bit
does not affect the reception of the control endpoint setup stage transaction.
6 ISO Isochronous endpoint The isochronous endpoint bit is set to a 1 by the MCU to specify the use of a
particular in endpoint for isochronous transactions. This bit should be cleared to a 0
by the MCU to use a particular in endpoint for control, interrupt, or bulk transactions.
5 TOGGLE Toggle The toggle bit is controlled by the UBM and is toggled at the end of a successful in
data stage transaction if a valid data packet is transmitted. If this bit is a 0, a DATA0
PID is transmitted in the data packet to the host PC. If this bit is a 1, a DATA1 PID is
transmitted in the data packet.
4 DBUF Double buffer mode The double buffer mode bit is set to a 1 by the MCU to enable the use of both the X
and Y data packet buffers for USB transactions to a particular in endpoint. This bit
should be cleared to a 0 by the MCU to use the single buffer mode. In the single
buffer mode, only the X buffer is used.
3 STALL Stall The stall bit is set to a 1 by the MCU to stall endpoint transactions. When this bit is
set, the hardware will automatically return a stall handshake to the host PC for any
transaction received for the endpoint.
2 IEPIE Interrupt enable The interrupt enable bit is set to a 1 by the MCU to enable the in endpoint interrupt.
See section A.5.7.2 for details on the in endpoint interrupts.
1:0 — Reserved Reserved for future use
