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TUSB3200ACPAH

Part # TUSB3200ACPAH
Description USB STREAMING CONTROLLER
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

A–10
A.4.3.6 USB Out Endpoint – Configuration Byte (OEPCNFx)
The USB out endpoint configuration byte contains the various bits used to configure and control the endpoint. Note
that the bits in this byte take on different functionality based on the type of endpoint defined. Basically, the control,
iInterrupt, and bulk endpoints function differently than the isochronous endpoints.
A.4.3.6.1 USB Out Endpoint – Control, Interrupt or Bulk configuration byte
This section defines the functionality of the bits in the USB out endpoint configuration byte for control, interrupt, and
bulk endpoints.
Bit 7 6 5 4 3 2 1 0
Mnemonic OEPEN ISO TOGGLE DBUF STALL OEPIE
Type R/W R/W R/W R/W R/W R/W R/W R/W
BIT MNEMONIC NAME DESCRIPTION
7 OEPEN Endpoint enable The endpoint enable bit is set to a 1 by the MCU to enable the out endpoint.
6 ISO Isochronous endpoint The isochronous endpoint bit is set to a 1 by the MCU to specify the use of a
particular out endpoint for isochronous transactions. This bit should be cleared to a 0
by the MCU to use a particular out endpoint for control, interrupt or bulk transactions.
5 TOGGLE Toggle The toggle bit is controlled by the UBM and is toggled at the end of a successful out
data stage transaction if a valid data packet is received and the data packet PID
matches the expected PID.
4 DBUF Double buffer mode The double buffer mode bit is set to a 1 by the MCU to enable the use of both the X
and Y data packet buffers for USB transactions to a particular out endpoint. This bit
should be cleared to a 0 by the MCU to use the single buffer mode. In the single
buffer mode, only the X buffer is used.
3 STALL Stall The stall bit is set to a 1 by the MCU to stall endpoint transactions. When this bit is
set, the hardware will automatically return a stall handshake to the host PC for any
transaction received for the endpoint. An exception is the control endpoint setup
stage transaction, which must always be received. This requirement allows a
Clear_Feature_Stall request to be received from the host PC. Control endpoint data
and status stage transactions however can be stalled. The stall bit is cleared to a 0
by the MCU if a Clear_Feature_Stall request or a USB reset is received from the host
PC. For a control write transaction, if the amount of data received is greater than
expected, the UBM will set the stall bit to a 1 to stall the endpoint. When the stall bit is
set to a 1 by the UBM, the USB out endpoint 0 interrupt will be generated.
2 OEPIE Interrupt enable The interrupt enable bit is set to a 1 by the MCU to enable the out endpoint interrupt.
See section A.5.7.1 for details on the out endpoint interrupts.
1:0 Reserved Reserved for future use
A–11
A.4.3.6.2 USB Out Endpoint – Isochronous Configuration Byte
This section defines the functionality of the bits in the USB out endpoint configuration byte for isochronous endpoints.
Bit 7 6 5 4 3 2 1 0
Mnemonic OEPEN ISO OVF BPS4 BPS3 BPS2 BPS1 BPS0
Type R/W R/W R/W R/W R/W R/W R/W R/W
BIT MNEMONIC NAME DESCRIPTION
7 OEPEN Endpoint enable The endpoint enable bit is set to a 1 by the MCU to enable the out endpoint.
6 ISO Isochronous endpoint The isochronous endpoint bit is set to a 1 by the MCU to specify the use of a
particular out endpoint for isochronous transactions. This bit should be cleared to a 0
by the MCU for a particular out endpoint to be used for control, interrupt, or bulk
transactions.
5 OVF Overflow The overflow bit is set to a 1 by the UBM to indicate a buffer overflow condition has
occurred. This bit is used for diagnostic purposes only and is not used for normal
operation. This bit can only be cleared to a 0 by the MCU.
4:0 BPS(4:0) Bytes per sample The bytes per sample bits are used to define the number of bytes per isochronous
data sample. In other words, the total number of bytes in an entire audio CODEC
frame. For example, a PCM 16-bit stereo audio data sample consists of 4 bytes.
There are two bytes of left channel data and two bytes of right channel data. For a
four channel system using 16-bit data, the total number of bytes would be 8, which
would be the isochronous data sample size.
00h = 1 byte, 01h = 2 bytes, , 1Fh = 32 bytes
A.4.4 USB In Endpoint Configuration Bytes
This section describes the individual bytes in the USB endpoint configuration blocks for the in endpoints. A set of 8
bytes is used for the control and operation of each USB in endpoint. In addition to the USB control endpoint, the
TUSB3200 supports up to a total of seven in endpoints.
A.4.4.1 USB In Endpoint – Y Buffer Data Count Byte (IEPDCNTYx)
The USB in endpoint Y buffer data count byte contains the 7-bit value used to specify the amount of data to be
transmitted in a data packet to the host PC. The no acknowledge status bit is also contained in this byte.
Bit 7 6 5 4 3 2 1 0
Mnemonic NACK DCNTY6 DCNTY5 DCNTY4 DCNTY3 DCNTY2 DCNTY1 DCNTY0
Type R/W R/W R/W R/W R/W R/W R/W R/W
BIT MNEMONIC NAME DESCRIPTION
7 NACK No acknowledge The no acknowledge status bit is set to a 1 by the UBM at the end of a successful
USB in transaction to this endpoint to indicate that the USB endpoint Y buffer is
empty. For control, interrupt, or bulk endpoints, when this bit is set to a 1, all
subsequent transactions to the endpoint will result in a NACK handshake response
to the host PC. Also for control, interrupt, and bulk endpoints, to enable this endpoint
to transmit another data packet to the Host PC, this bit must be cleared to a 0 by the
MCU. For isochronous endpoints, a NACK handshake response to the host PC is
not allowed. Therefore, the UBM ignores this bit in reference to sending the next
data packet. However, the MCU or DMA should clear this bit after writing a data
packet to the buffer.
6:0 DCNTY(6:0) Y Buffer data count The Y buffer data count value is set by the MCU or DMA when a new data packet is
written to the Y buffer for the in endpoint. The 7-bit value is set to the number of bytes
in the data packet for control, interrupt, or bulk endpoint transfers and is set to the
number of samples in the data packet for isochronous endpoint transfers. To
determine the number of samples in the data packet for isochronous transfers, the
bytes per sample value in the configuration byte is used.
A–12
A.4.4.2 USB In Endpoint – Y Buffer Base Address Byte (IEPBBAYx)
The USB in endpoint Y buffer base address byte contains the 8-bit value used to specify the base memory location
for the Y data buffer for a particular USB in endpoint.
Bit 7 6 5 4 3 2 1 0
Mnemonic BBAY10 BBAY9 BBAY8 BBAY7 BBAY6 BBAY5 BBAY4 BBAY3
Type R/W R/W R/W R/W R/W R/W R/W R/W
BIT MNEMONIC NAME DESCRIPTION
7:0 BBAY(10:3) Y Buffer base address The Y buffer base address value is set by the MCU to program the base address
location in memory to be used for the Y data buffer. A total of 11 bits is used to specify
the base address location. This byte specifies the most significant 8 bits of the
address. All 0s are used by the hardware for the three least significant bits.
A.4.4.3 USB In Endpoint – X Buffer Data Count Byte (IEPDCNTXx)
The USB in endpoint X buffer data count byte contains the 7-bit value used to specify the amount of data received
in a data packet from the host PC. The no acknowledge status bit is also contained in this byte.
Bit 7 6 5 4 3 2 1 0
Mnemonic NACK DCNTX6 DCNTX5 DCNTX4 DCNTX3 DCNTX2 DCNTX1 DCNTX0
Type R/W R/W R/W R/W R/W R/W R/W R/W
BIT MNEMONIC NAME DESCRIPTION
7 NACK No acknowledge The no acknowledge status bit is set to a 1 by the UBM at the end of a successful
USB in transaction to this endpoint to indicate that the USB endpoint X buffer is
empty. For control, interrupt, or bulk endpoints, when this bit is set to a 1, all
subsequent transactions to the endpoint will result in a NACK handshake response
to the host PC. Also for control, interrupt, and bulk endpoints, to enable this endpoint
to transmit another data packet to the host PC, this bit must be cleared to a 0 by the
MCU. For isochronous endpoints, a NACK handshake response to the host PC is
not allowed. Therefore, the UBM ignores this bit in reference to sending the next
data packet. However, the MCU or DMA should clear this bit after writing a data
packet to the buffer.
6:0 DCNTX(6:0) X Buffer data count The X buffer data count value is set by the MCU or DMA when a new data packet is
written to the X buffer for the in endpoint. The 7-bit value is set to the number of bytes
in the data packet for control, interrupt, or bulk endpoint transfers and is set to the
number of samples in the data packet for isochronous endpoint transfers. To
determine the number of samples in the data packet for isochronous transfers, the
bytes per sample value in the configuration byte is used.
A.4.4.4 USB In Endpoint – X and Y Buffer Size Byte (IEPBSIZx)
The USB in endpoint X and Y buffer size byte contains the 8-bit value used to specify the size of the two data buffers
to be used for this endpoint.
Bit 7 6 5 4 3 2 1 0
Mnemonic BSIZ7 BSIZ6 BSIZ5 BSIZ4 BSIZ3 BSIZ2 BSIZ1 BSIZ0
Type R/W R/W R/W R/W R/W R/W R/W R/W
BIT MNEMONIC NAME DESCRIPTION
7 BSIZ(7:0) Buffer size The X and Y buffer size value is set by the MCU to program the size of the X and Y
data packet buffers. Both buffers are programmed to the same size based on this
value. This value should be in 8 byte units. For example, a value of 18h would result
in the size of the X and Y buffers each being set to 192 bytes.
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