2–21

The I

S protocol does not provide for command/status data transfers. Therefore, when using the TUSB3200 device

with a CODEC that uses an I

S serial interface for audio data transfers, the TUSB3200 I

C serial interface can be

used for CODEC command/status data transfers.

In addition, the TUSB3200 CODEC port interface is very flexible. As a result, many variations of the serial interface

protocol can be configured including an SCLK-to-LRCK ratio of 32.

2.2.13.3.1 Mapping of DMA Time Slots to CODEC Port Interface Time Slots for I

S Modes

The I

S serial data format requires two time slots (left channel and right channel) for each serial data output or input.

As discussed in the previous section, the TUSB3200 can support multiple serial data outputs and/or inputs at the

same time in accordance with Table 2–5. Each of the serial data outputs and/or inputs has a unique left channel time

slot (slot number 0) and right channel time slot (slot number 1). For the I

S modes of operation, the DMA channel

time slot assignments must be mapped to the different left channel and right channel time slots for the serial data

outputs and inputs. Each DMA channel has fourteen time slot bits, which are time slot assignment bits 0 through 13.

Table 2–6 and 2–7 show the CODEC port interface time slot numbers and the corresponding time slot numbers for

the DMA channels.

As an example, suppose that CODEC port interface mode 4 is to be used with three serial data outputs and one serial

data input. The DMA channel to be programmed to support the three serial data outputs would need to have time

slot assignment bits 0, 1,2, 4, 5, and 6 set to a 1. The DMA channel to be programmed to support the serial data input

would need to have time slot assignment bits 0 and 4 set to a 1.

Table 2–6. SLOT Assignments for CODEC Port Interface I

S Mode (Output)

SERIAL DATA OUTPUT

CODEC PORT INTERFACE TIME SLOT NUMBER DMA CHANNELS(s) TIME SLOT NUMBER

SERIAL

DATA

OUTPUT

LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL

SDOUT1 0 1 0 4

SDOUT2 0 1 1 5

SDOUT3 0 1 2 6

SDOUT4 0 1 3 7

Table 2–7. SLOT Assignments for CODEC Port Interface I

S Mode (Input)

SERIAL DATA INPUT

CODEC PORT INTERFACE TIME SLOT NUMBER DMA CHANNELS(s) TIME SLOT NUMBER

SERIAL

DATA

INPUT

LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL

SDIN1 0 1 0 4

SDIN2 0 1 1 5

SDIN3 0 1 2 6

2–22

2.2.13.4General-Purpose Mode of Operation

In the general-purpose mode the CODEC port interface can be configured to various user defined serial interface

formats using the pin assignments shown in Table 2–8. This mode gives the user the flexibility to configure the

TUSB3200 to connect to various CODECs and DSPs that do not use a standard serial interface format.

Table 2–8. Terminal Assignments for CODEC Port Interface General-Purpose Mode

TERMINAL

NO. NAME

MODE 0

35 CSYNC CSYNC I/O

34 CSCLK CSCLK I/O

36 CDATO CDAT0 O

38 CDATI CDAT1 I

39 CRESET CRESET O

40 CSCHNE NC O

2.2.14 I

C Interface

The TUSB3200 has a bidirectional two-wire serial interface that can be used to access other ICs. This serial interface

is compatible with the I

C (Inter IC) bus protocol and supports both 100-kbps and 400-kbps data transfer rates. The

TUSB3200 is a master only device that does not support a multimaster bus environment (no bus arbitration) or wait

state insertion. Hence this interface can be used to access I

C slave devices including EEPROMs and CODECs. For

example, if the application program code is stored in an EEPROM on the PCB, then the MCU will download the code

from the EEPROM to the TUSB3200 on-chip RAM using the I

C interface. Another example is the control of a CODEC

device that uses an I

S interface for audio data transfers and an I

C interface for control register read/write access.

2.2.14.1Data Transfers

The two-wire serial interface uses the serial clock signal, SCL, and the serial data signal, SDA. As stated above, the

TUSB3200 is a master only device, and therefore, the SCL signal is an output only. The SDA signal is a bidirectional

signal that uses an open-drain output to allow the TUSB3200 to be wire-ORed with other devices that use open-drain

or open-collector outputs.

All read and write data transfers on the serial bus are initiated by a master device. The master device is also

responsible for generating the clock signal used for all data transfers. The data is transferred on the bus serially one

bit at a time. However, the protocol requires that the address and data be transferred in byte (8-bit) format with the

most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the

receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start

condition on the bus and ends with the master device driving a stop condition on the bus.

The timing relationship between the SCL and SDA signals for each bit transferred on the bus is shown in Figure 3-7.

As shown, the SDA signal must be stable while the SCL signal is high, which also means that the SDA signal can

only change states while the SCL signal is low.

The timing relationship between the SCL and SDA signals for the start and stop conditions is shown in Figure 3-8.

As shown, the start condition is defined as a high-to-low transition of the SDA signal while the SCL signal is high. Also

as shown, the stop condition is defined as a low-to-high transition of the SDA signal while the SCL signal is high.

When the TUSB3200 is the device receiving data information, the TUSB3200 will acknowledge each byte received

by driving the SDA signal low during the acknowledge SCL period. During the acknowledge SCL period, the slave

device must stop driving the SDA signal. If the TUSB3200 is unable to receive a byte, the SDA signal will not be driven

low and should be pulled high external to the TUSB3200 device. A high during the SCL period indicates a

not-acknowledge to the slave device. The acknowledge timing is shown in Figure 3-9.

Read and write data transfers by the TUSB3200 device can be done using single byte or multiple byte data transfers.

Therefore, the actual transfer type used depends on the protocol required by the I

C slave device being accessed.

2–23

2.2.14.2Single Byte Write

As shown is Figure 2-4, a single byte data write transfer begins with the master device transmitting a start condition

followed by the I

C device address and the read/write bit. The read/write bit determines the direction of the data

transfer. For a write data transfer, the read/write bit should be a 0. After receiving the correct I

C device address and

the read/write bit, the I

C slave device should respond with an acknowledge bit. Next, the TUSB3200 should transmit

the address byte or bytes corresponding to the I

C slave device internal memory address being accessed. After

receiving the address byte, the I

C slave device should again respond with an acknowledge bit. Next, the TUSB3200

device should transmit the data byte to be written to the memory address being accessed. After receiving the data

byte, the I

C slave device should again respond with an acknowledge bit. Finally, the TUSB3200 device should

transmit a stop condition to complete the single byte data write transfer.

A6 A5 A4 A3 A2 A1 A0

R/W

ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

Start Condition

Stop

Condition

Acknowledge Acknowledge Acknowledge

C Device Address and

Read/Write Bit

Memory or Register Address Data Byte

SDA

Figure 2–4. Single Byte Write Transfer

2.2.14.3Multiple Byte Write

A multiple byte data write transfer is identical to a single byte data write transfer except that multiple data bytes are

transmitted by the TUSB3200 device to the I

C slave device as shown in Figure 2-5. After receiving each data byte,

the I

C slave device should respond with an acknowledge bit.

D7 D6 D1 D0 ACK

Stop

Condition

Acknowledge

C Device Address and

Read/Write Bit

Memory or Register Address Last Data Byte

A6 A5 A1 A0

R/W

ACK A7 A5 A1 A0 ACK D7 D6 D1 D0 ACK

Start Condition

Acknowledge Acknowledge Acknowledge

SDA

First Data Byte

A4 A3A6

Other

Data Bytes

Figure 2–5. Multiple Byte Write Transfer

2.2.14.4Single Byte Read

As shown in Figure 2-6, a single byte data read transfer begins with the TUSB3200 device transmitting a start

condition followed by the I

C device address and the read/write bit. For the data read transfer, both a write followed

by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory

address to be read. As a result, the read/write bit should be a 0. After receiving the I

C device address and the

read/write bit, the I

C slave device should respond with an acknowledge bit. Also, after sending the internal memory

address byte or bytes, the TUSB3200 device should transmit another start condition followed by the I

C slave device

address and the read/write bit again. This time the read/write bit should be a 1 indicating a read transfer. After

receiving the I

C device address and the read/write bit the I

C slave device should again respond with an

acknowledge bit. Next, the I

C slave device should transmit the data byte from the memory address being read. After

receiving the data byte, the TUSB3200 device should transmit a not-acknowledge followed by a stop condition to

complete the single byte data read transfer.

A6 A5 A0 R/W ACK A7 A6 A5 A4 A0 ACK A6 A5 A0 ACK

Start

Condition

Stop

Condition

Acknowledge Acknowledge Acknowledge

C Device Address and

Read/Write Bit

Memory or Register Address Data Byte

SDA

D7 D6 D1 D0 ACK

C Device Address and

Read/Write Bit

Repeat Start Condition

Not

Acknowledge

R/WA1 A1

Figure 2–6. Single Byte Read Transfer

Part #	TUSB3200ACPAH
Description	USB STREAMING CONTROLLER
Category	IC
Availability	Out of Stock
Qty	0

TUSB3200ACPAH

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