3−15

3.20 Miscellaneous Configuration Register

The miscellaneous configuration register provides miscellaneous PCI-related configuration. See Table 3−17 for a

complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Miscellaneous configuration

Type R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Miscellaneous configuration

Type R/W R R/W R R R/W R R R R R R/W R/W R/W R/W R/W

Default 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0

Type: Read/Write, Read-only

Offset: F0h

Default: 0000 2400h

Table 3−17. Miscellaneous Configuration Register

BIT FIELD NAME TYPE DESCRIPTION

31−16 RSVD R Reserved. Bits 31−16 return 0s when read.

15 PME_D3COLD R/W PCI_PME support from D3

cold

. This bit programs bit 15 (PME_D3COLD) in the power

management capabilities register at offset 46h in PCI configuration space (see Section 3.17,

Power Management Capabilities Register).

14 RSVD R Reserved. Bit 14 returns 0 when read.

13 PME_SUPPORT_D2 R/W PCI_PME support. This bit programs bit 13 (PME_SUPPORT_D2) in the power management

capabilities register at offset 46h in PCI configuration space (see Section 3.17, Power

Management Capabilities Register). If wake up from the D2 power state implemented in the

TSB12LV26 device is not desired, this bit is cleared to indicate to power-management software

that wake-up from D2 is not supported.

12−11 RSVD R Reserved. Bits 12 and 11 return 0s when read.

10 D2_SUPPORT R/W D2 support. This bit programs bit 10 (D2_SUPPORT) in the power management capabilities

Capabilities Register). If the D2 power state in the TSB12LV26 device is not desired, this bit is

cleared to indicate to power-management software that D2 is not supported.

9−5 RSVD R Reserved. Bits 9−5 return 0s when read.

4 DIS_TGT_ABT R/W Bit 4 defaults to 0, which provides OHCI-Lynxt compatible target abort signaling. When this bit is

set to 1, it enables the no-target-abort mode, in which the TSB12LV26 device returns

indeterminate data instead of signaling target abort.

The link is divided into the PCI_CLK and SCLK domains. If software tries to access registers in the

link that are not active because the SCLK is disabled, a target abort is issued by the link. On some

systems, this can cause a problem resulting in a fatal system error. Enabling this bit allows the link

to respond to these types of requests by returning FFh.

It is recommended that this bit be set to 1.

3 GP2IIC R/W When bit 3 is set to 1, the GPIO3 and GPIO2 signals are internally routed to the SCL and SDA,

respectively. The GPIO3 and GPIO2 terminals are also placed in a high-impedance state.

2 DISABLE_SCLKGATE R/W When bit 2 is set to 1, the internal SCLK runs identically with the chip input. This is a test feature

only and must be cleared to 0 (all applications).

1 DISABLE_PCIGATE R/W When bit 1 is set to 1, the internal PCI clock runs identically with the chip input. This is a test feature

only and must be cleared to 0 (all applications).

0 KEEP_PCLK R/W When bit 0 is set to 1, the PCI clock is always kept running through the PCI_CLKRUN protocol.

When this bit is cleared, the PCI clock can be stopped using PCI_CLKRUN

3−16

3.21 Link Enhancement Control Register

The link enhancement control register implements TI proprietary bits that are initialized by software or by a serial

EEPROM, if present. After these bits are set to 1, their functionality is enabled only if bit 22 (aPhyEnhanceEnable)

in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is

set to 1. See Table 3−18 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Link enhancement control

Type R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Link enhancement control

Type R R R/W R/W R R R R R/W R R R R R/W R/W R

Default 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0

Type: Read/Write, Read-only

Offset: F4h

Default: 0000 1000h

Table 3−18. Link Enhancement Control Register Description

BIT FIELD NAME TYPE DESCRIPTION

31−14 RSVD R Reserved. Bits 31−14 return 0s when read.

13−12 atx_thresh R/W This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the

TSB12LV26 device retries the packet, it uses a 2K-byte threshold, resulting in a store-and-forward

operation.

00 = Threshold ~ 2K bytes resulting in a store-and-forward operation

01 = Threshold ~ 1.7K bytes (default)

10 = Threshold ~ 1K bytes

11 = Threshold ~ 512 bytes

These bits fine-tune the asynchronous transmit threshold. For most applications the 1.7-K threshold

is optimal. Changing this value may increase or decrease the 1394 latency depending on the average

PCI bus latency.

Setting the AT threshold to 1.7K, 1K, or 512 bytes results in data being transmitted at these thresholds

or when an entire packet has been checked into the FIFO. If the packet to be transmitted is larger than

the AT threshold, the remaining data must be received before the AT FIFO is emptied; otherwise, an

underrun condition will occur, resulting in a packet error at the receiving node. As a result, the link will

then commence store-and-forward operation—that is, wait until it has the complete packet in the FIFO

before retransmitting it on the second attempt, to ensure delivery.

An AT threshold of 2K results in store-and-forward operation, which means that asynchronous data

will not be transmitted until an end-of-packet token is received. Restated, setting the AT threshold to

2K results in only complete packets being transmitted.

Note that this device always uses store-and-forward when the asynchronous transmit retries register

at OHCI offset 08h (see Section 4.3, Asynchronous Transmit Retries Register) is cleared.

11−8 RSVD R Reserved. Bits 11−8 return 0s when read.

7 enab_unfair R/W Enable asynchronous priority requests. OHCI-Lynxt compatible. Setting bit 7 to 1 enables the link to

respond to requests with priority arbitration. It is recommended that this bit be set to 1.

6 RSVD R This bit is not assigned in the TSB12LV26 follow-on products, since this bit location loaded by the serial

EEPROM from the enhancements field corresponds to bit 23 (programPhyEnable) in the host

controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register).

5−3 RSVD R Reserved. Bits 5−3 return 0s when read.

3−17

Table 3−18. Link Enhancement Control Register Description (Continued)

BIT FIELD NAME TYPE DESCRIPTION

2 enab_insert_idle R/W Enable insert idle. OHCI-Lynxt compatible. When the PHY device has control of the PHY_CTL0 and

PHY_CTL1 control lines and the PHY_DATA0−PHY_DATA7 data lines and the link requests control,

the PHY device drives 11b on the PHY_CTL0 and PHY_CTL1 lines. The link can then start driving

these lines immediately. Setting bit 2 to 1 inserts an idle state, so the link waits one clock cycle before

it starts driving the lines (turnaround time). It is recommended that this bit be set to 1.

1 enab_accel R/W Enable acceleration enhancements. OHCI-Lynxt compatible. When bit 1 is set to 1, the PHY device

is notified that the link supports the IEEE 1394a-2000 acceleration enhancements, that is,

ack-accelerated, fly-by concatenation, etc. It is recommended that this bit be set to 1.

0 RSVD R Reserved. Bit 0 returns 0 when read.

3.22 Subsystem Access Register

Write access to the subsystem access register updates the subsystem identification registers identically to

OHCI-Lynxt. The system ID value written to this register may also be read back from this register. See Table 3−19

for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Subsystem access

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Subsystem access

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Type: Read/Write

Offset: F8h

Default: 0000 0000h

Table 3−19. Subsystem Access Register Description

BIT FIELD NAME TYPE DESCRIPTION

31−16 SUBDEV_ID R/W Subsystem device ID alias. This field indicates the subsystem device ID.

15−0 SUBVEN_ID R/W Subsystem vendor ID alias. This field indicates the subsystem vendor ID.

Part #	TSB12LV26TPZEP
Description	V62/03627-01XE -OHCI-LYNX PCI-BASED - Trays
Category	IC
Availability	In Stock
Qty	2

TSB12LV26TPZEP

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