3−12

3.17 Power Management Capabilities Register

The power management capabilities register indicates the capabilities of the TSB12LV26 device related to PCI power

management. See Table 3−14 for a complete description of the register contents.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Power management capabilities

Type RU RU RU RU RU RU R R R R R R R R R R

Default 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1

Type: Read/Update, Read-only

Offset: 46h

Default: 6401h

Table 3−14. Power Management Capabilities Register Description

BIT FIELD NAME TYPE DESCRIPTION

15 PME_D3COLD RU PCI_PME support from D3

cold

. This bit can be set to 1 or cleared to 0 via bit 15 (PME_D3COLD) in

the miscellaneous configuration register at offset F0h in the PCI configuration space (see Section 3.20,

Miscellaneous Configuration Register). The miscellaneous configuration register is loaded from ROM.

When this bit is set to 1, it indicates that the TSB12LV26 device is capable of generating a PCI_PME

wake event from D3

cold

. This bit state is dependent upon the TSB12LV26 V

AUX

implementation and

may be configured by using bit 15 (PME_D3COLD) in the miscellaneous configuration register.

14−11 PME_SUPPORT RU PCI_PME support. This 4-bit field indicates the power states from which the TSB12LV26 device may

assert PCI_PME

. This field returns a value of 1100b by default, indicating that PCI_PME may be

asserted from the D3

hot

and D2 power states. Bit 13 may be modified by host software using bit 13

(PME_SUPPORT_D2) in the miscellaneous configuration register at offset F0h in the PCI

configuration space (see Section 3.20, Miscellaneous Configuration Register).

10 D2_SUPPORT RU D2 support. This bit can be set or cleared via bit 10 (D2_SUPPORT) in the miscellaneous configuration

set to 1, it indicates that D2 support is present. When this bit is cleared, it indicates that D2 support

is not present for backward compatibility with the TSB12LV22 device. For normal operation, this bit is

set to 1.

9 D1_SUPPORT R D1 support. Bit 9 returns a 0 when read, indicating that the TSB12LV26 device does not support the

D1 power state.

8 DYN_DATA R Dynamic data support. Bit 8 returns a 0 when read, indicating that the TSB12LV26 device does not

report dynamic power-consumption data.

7−6 RSVD R Reserved. Bits 7 and 6 return 0s when read.

5 DSI R Device-specific initialization. Bit 5 returns 0 when read, indicating that the TSB12LV26 device does not

require special initialization beyond the standard PCI configuration header before a generic class

driver is able to use it.

4 AUX_PWR R Auxiliary power source. Since the TSB12LV26 device does not support PCI_PME generation in the

cold

device state, bit 4 returns 0 when read.

3 PME_CLK R PME clock. Bit 3 returns 0 when read, indicating that no host bus clock is required for the TSB12LV26

device to generate PCI_PME

2−0 PM_VERSION R Power-management version. This field returns 001b when read, indicating that the TSB12LV26 device

is compatible with the registers described in the PCI Bus Power Management Interface Specification

(Revision 1.0).

3−13

3.18 Power Management Control and Status Register

The power management control and status register implements the control and status of the PCI power management

function. This register is not affected by the internally generated reset caused by the transition from the D3

hot

to D0

state. See Table 3−15 for a complete description of the register contents.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Power management control and status

Type RC R R R R R R R/W R R R R R R R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Type: Read/Clear, Read/Write, Read-only

Offset: 48h

Default: 0000h

Table 3−15. Power Management Control and Status Register Description

BIT FIELD NAME TYPE DESCRIPTION

15 PME_STS RC Bit 15 is set to 1 when the TSB12LV26 device normally asserts the PCI_PME signal, independent of

the state of bit 8 (PME_ENB). This bit is cleared by a writeback of 1, which also clears the PCI_PME

signal driven by the TSB12LV26 device. Writing a 0 to this bit has no effect.

14−9 DYN_CTRL R Dynamic data control. This field returns 0s when read since the TSB12LV26 device does not report

dynamic data.

8 PME_ENB R/W When bit 8 is set to 1, PCI_PME assertion is enabled. When bit 8 is cleared, PCI_PME assertion is

disabled. This bit defaults to 0 if the function does not support PCI_PME

generation from D3

cold

. If the

function supports PCI_PME

from D3

cold

, this bit is sticky and must be explicitly cleared by the operating

system each time it is initially loaded. Functions that do not support PCI_PME

generation from any

D-state (that is, bits 15−11 in the power management capabilities register at offset 46h in PCI

configuration space (see Section 3.17, Power Management Capabilities Register) equal 00000b), may

hardwire this bit to be read-only, always returning a 0 when read by system software.

7−5 RSVD R Reserved. Bits 7−5 return 0s when read.

4 DYN_DATA R Dynamic data. Bit 4 returns 0 when read since the TSB12LV26 device does not report dynamic data.

3−2 RSVD R Reserved. Bits 3 and 2 return 0s when read.

1−0 PWR_STATE R/W Power state. This 2-bit field sets the TSB12LV26 device power state and is encoded as follows:

00 = Current power state is D0.

01 = Current power state is D1 (not supported by this device).

10 = Current power state is D2.

11 = Current power state is D3

hot

3−14

3.19 Power Management Extension Register

The power management extension register provides extended power management features not applicable to the

TSB12LV26 device; thus, it is read-only and returns 0s when read. See Table 3−16 for a complete description of the

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Power management extension

Type R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Type: Read-only

Offset: 4Ah

Default: 0000h

Table 3−16. Power Management Extension Register Description

BIT FIELD NAME TYPE DESCRIPTION

15−8 PM_DATA R Power management data. This field returns 00h when read since the TSB12LV26 device does not

report dynamic data.

7−0 PMCSR_BSE R Power management CSR − bridge support extensions. This field returns 00h when read since the

TSB12LV26 device does not provide P2P bridging.

Part #	TSB12LV26TPZEP
Description	V62/03627-01XE -OHCI-LYNX PCI-BASED - Trays
Category	IC
Availability	In Stock
Qty	2

TSB12LV26TPZEP

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