7−3
7.3 Electrical Characteristics Over Recommended Operating Conditions (unless
otherwise noted)
OPERATION
TEST
CONDITIONS
MIN MAX UNIT
I
OH
= − 0.5 mA 0.9 V
CC
PCI
I
OH
= − 2 mA 2.4
V
High-level output voltage
I
OH
= − 4 µA 2.8
V
High-level output voltage
PHY interface
I
OH
= − 8 mA V
CC
− 0.6
Miscellaneous
‡
I
OH
= − 4 mA V
CC
− 0.6
I
OL
= 1.5 mA 0.1 V
CC
PCI
I
OL
= 6 mA 0 0.55
V
†
Low-level output voltage
I
OL
= 4 mA 0.4
V
PHY interface
I
OL
= 8 mA
Miscellaneous
‡
I
OL
= 4 mA 0.5
I
OZ
3-state output high-impedance Output pins 3.6 V V
O
= V
CC
or GND ±20 µA
Input pins 3.6 V V
I
= GND
‡
±20
I
IL
Low-level input current
I/O pins
†
3.6 V V
I
= GND
‡
±20
µA
PCI
†
3.6 V V
I
= V
CC
‡
±20
IH
Others
†
3.6 V V
I
= V
CC
‡
±20
µ
†
For I/O terminals, input leakage (I
IL
and I
IH
) includes I
OZ
of the disabled output.
‡
Miscellaneous terminals are: GPIO2 (2), GPIO3 (3), SDA (5), SCL (4), CYCLEOUT (77).
7.4 Switching Characteristics for PCI Interface
§
PARAMETER MEASURED MIN MAX UNIT
t
su
Setup time before PCLK −50% to 50% 7 ns
t
h
Hold time before PCLK −50% to 50% 0 ns
t
val
Delay time, PHY_CLK to data valid −50% to 50% 2 11 ns
§
These parameters are ensured by design.
7.5 Switching Characteristics for PHY-Link Interface
§
PARAMETER MEASURED MIN MAX UNIT
t
su
Setup time, Dn, CTLn, LREQ to PHY_CLK −50% to 50% 6 ns
t
h
Hold time, Dn, CTLn, LREQ before PHY_CLK −50% to 50% 0 ns
t
d
Delay time, PHY_CLK to Dn, CTLn −50% to 50% 2 11 ns
§
These parameters are ensured by design.
