6−1

6 Serial EEPROM Interface

The TSB12LV26 device provides a serial bus interface to initialize the 1394 global unique ID register and a few PCI

configuration registers through a serial EEPROM. The TSB12LV26 device communicates with the serial EEPROM

via the 2-wire serial interface.

After power up the serial interface initializes the locations listed in Table 6−1. While the TSB12LV26 device is

accessing the serial EEPROM, all incoming PCI slave accesses are terminated with retry status. Table 6−2 shows

the serial EEPROM memory map required for initializing the TSB12LV26 registers.

NOTE: If a ROM is implemented in the design, it must be programmed. An unprogrammed

ROM defaults to all 1s, which adversely impacts device operation.

Table 6−1. Registers and Bits Loadable Through Serial EEPROM

EEPROM OFFSET

OHCI/PCI

CONFIGURATION

OFFSET

BITS LOADED

FROM EEPROM

00h PCI register (3Eh) PCI maximum latency, PCI minimum grant 15−0

01h PCI register (2Dh) PCI vendor ID 15−0

03h PCI register (2Ch) PCI subsystem ID 15−0

05h (bit 6) OHCI register (50h) Host controller control 23

05h PCI register (F4h) Link enhancements control 7, 2, 1

06h−0Ah OHCI register (24h) GUID high 31−0

0Bh−0Eh OHCI register(28h) GUID low 31−0

10h PCI register (F4h) Link enhancements control 13, 12

11h−12h PCI register (F0h) PCI miscellaneous 15, 13, 10, 4−0

13h PCI register (40h) PCI OHCI 0

6−2

Table 6−2. Serial EEPROM Map

BYTE

ADDRESS

BYTE DESCRIPTION

00 PCI maximum latency (0h) PCI minimum grant (0h)

01 PCI vendor ID

02 PCI vendor ID (msbyte)

03 PCI subsystem ID (lsbyte)

04 PCI subsystem ID

[7]

Link_enhancement-

Control.enab_unfair

[6]

HCControl.

ProgramPhy

Enable

[5−3]

RSVD

[2]

Link_enhancement-

Control.enab_

insert_idle

[1]

Link_enhancement-

Control.enab_accel

[0]

RSVD

06 Mini ROM address

07 GUID high (lsbyte 0)

08 GUID high (byte 1)

09 GUID high (byte 2)

0A GUID high (msbyte 3)

0B GUID low (lsbyte 0)

0C GUID low (byte 1)

0D GUID low (byte 2)

0E GUID low (msbyte 3)

0F Checksum

[15−14]

RSVD

[13−12]

AT threshold

[11−8]

RSVD

[7−5]

RSVD

[4]

Disable

Target

Abort

[3]

GP2IIC

[2]

Disable SCLK gate

[1]

Disable PCI gate

[0]

Keep PCI

[15]

PME D3 Cold

[14]

RSVD

[13]

PME

Support

[12−11]

RSVD

[10]

D2 support

[9−8]

RSVD

[7−1]

RSVD

[0]

Global

swap

14 RSVD

15−1E RSVD

1F RSVD

7−1

7 Electrical Characteristics

7.1 Absolute Maximum Ratings Over Operating Temperature Ranges

†

Supply voltage range, V

−0.5 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage range, V

CCP

−0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range for PCI, V

−0.5 to V

CCP

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range for miscellaneous and PHY interface, V

−0.5 to V

CCI

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . .

Output voltage range for PCI, V

−0.5 to V

CCP

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range for miscellaneous and PHY interface, V

−0.5 to V

CCP

+ 0.5 V. . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

< 0 or V

> V

) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

< 0 or V

> V

) (see Note 2) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range −40°C to 110°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Applies to external input and bidirectional buffers. V

> V

CCP

2. Applies to external output and bidirectional buffers. V

> V

CCP

Part #	TSB12LV26TPZEP
Description	V62/03627-01XE -OHCI-LYNX PCI-BASED - Trays
Category	IC
Availability	In Stock
Qty	2

TSB12LV26TPZEP

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