4−27

4.29 Node Identification Register

The node identification register contains the address of the node on which the OHCI-Lynxt chip resides, and

indicates the valid node number status. The 16-bit combination of the busNumber field (bits 15−6) and the

NodeNumber field (bits 5−0) is referred to as the node ID. See Table 4−21 for a complete description of the register

contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Node identification

Type RU RU R R RU R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Node identification

Type RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RU RU RU RU RU RU

Default 1 1 1 1 1 1 1 1 1 1 X X X X X X

Type: Read/Write/Update, Read/Update, Read-only

Offset: E8h

Default: 0000 FFXXh

Table 4−21. Node Identification Register Description

BIT FIELD NAME TYPE DESCRIPTION

31 iDValid RU Bit 31 indicates whether or not the TSB12LV26 device has a valid node number. It is cleared when a

1394 bus reset is detected, and set to 1 when the TSB12LV26 device receives a new node number

from the PHY device.

30 root RU Bit 30 is set to 1 during the bus reset process if the attached PHY device is root.

29−28 RSVD R Reserved. Bits 29 and 28 return 0s when read.

27 CPS RU Bit 27 is set to 1 if the PHY device is reporting that cable power status is OK.

26−16 RSVD R Reserved. Bits 26−16 return 0s when read.

15−6 BusNumber RWU This field identifies the specific 1394 bus the TSB12LV26 device belongs to when multiple

1394-compatible buses are connected via a bridge.

5−0 NodeNumber RU This field is the physical node number established by the PHY device during self-ID. It is automatically

set to the value received from the PHY device after the self-ID phase. If the PHY device sets the

NodeNumber to 63, software must not set bit 15 (run) in the asynchronous context control register (see

Section 4.37, Asynchronous Context Control Register) for either of the AT DMA contexts.

4−28

4.30 PHY Layer Control Register

The PHY layer control register reads or writes a PHY register. See Table 4−22 for a complete description of the

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name PHY layer control

Type RU R R R RU RU RU RU RU RU RU RU RU RU RU RU

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name PHY layer control

Type RWU RWU R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Type: Read/Write/Update, Read/Write, Read/Update, Read-only

Offset: ECh

Default: 0000 0000h

Table 4−22. PHY Layer Control Register Description

BIT FIELD NAME TYPE DESCRIPTION

31 rdDone RU Bit 31 is cleared to 0 by the TSB12LV26 device when either bit 15 (rdReg) or bit 14 (wrReg) is set to

1. This bit is set to 1 when a register transfer is received from the PHY device.

30−28 RSVD R Reserved. Bits 30−28 return 0s when read.

27−24 rdAddr RU This field is the address of the register most recently received from the PHY device.

23−16 rdData RU This field is the contents of a PHY register that has been read.

15 rdReg RWU Bit 15 is set to 1 by software to initiate a read request to a PHY register, and is cleared by hardware

when the request has been sent. Bits 14 (wrReg) and 15 (rdReg) must not both be set to 1

simultaneously.

14 wrReg RWU Bit 14 is set to 1 by software to initiate a write request to a PHY register, and is cleared by hardware

when the request has been sent. Bits 14 (wrReg) and 15 (rdReg) must not both be set to 1

simultaneously.

13−12 RSVD R Reserved. Bits 13 and 12 return 0s when read.

11−8 regAddr R/W This field is the address of the PHY register to be written or read.

7−0 wrData R/W This field is the data to be written to a PHY register and is ignored for reads.

4−29

4.31 Isochronous Cycle Timer Register

The isochronous cycle timer register indicates the current cycle number and offset. When the TSB12LV26 device is

cycle master, this register is transmitted with the cycle start message. When the TSB12LV26 device is not cycle

master, this register is loaded with the data field in an incoming cycle start. In the event that the cycle start message

is not received, the fields can continue incrementing on their own (if programmed) to maintain a local time reference.

See Table 4−23 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Isochronous cycle timer

Type RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU

Default X X X X X X X X X X X X X X X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Isochronous cycle timer

Type RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU

Default X X X X X X X X X X X X X X X X

Type: Read/Write/Update

Offset: F0h

Default: XXXX XXXXh

Table 4−23. Isochronous Cycle Timer Register Description

BIT FIELD NAME TYPE DESCRIPTION

31−25 cycleSeconds RWU This field counts seconds [rollovers from bits 24−12 (cycleCount field)] modulo 128.

24−12 cycleCount RWU This field counts cycles [rollovers from bits 11−0 (cycleOffset field)] modulo 8000.

11−0 cycleOffset RWU This field counts 24.576-MHz clocks modulo 3072, that is, 125 µs. If an external 8-kHz clock

configuration is being used, this field must be cleared to 0 at each tick of the external clock.

Part #	TSB12LV26TPZEP
Description	V62/03627-01XE -OHCI-LYNX PCI-BASED - Trays
Category	IC
Availability	In Stock
Qty	2

TSB12LV26TPZEP

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