4−24

4.25 Isochronous Receive Interrupt Event Register

The isochronous receive interrupt event set/clear register reflects the interrupt state of the isochronous receive

contexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_* command completes

and its interrupt bits are set to 1. Upon determining that the isochRx (bit 7) interrupt in the interrupt event register at

OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) has occurred, software can check this register to

determine which context(s) caused the interrupt. The interrupt bits are set to 1 by the asserting edge of the

corresponding interrupt signal, or by writing a 1 to the corresponding bit in the set register. The only mechanism to

clear a bit in this register is to write a 1 to the corresponding bit in the clear register. See Table 4−18 for a complete

description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Isochronous receive interrupt event

Type R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Isochronous receive interrupt event

Type R R R R R R R R R R R R RSC RSC RSC RSC

Default 0 0 0 0 0 0 0 0 0 0 0 0 X X X X

Type: Read/Set/Clear, Read-only

Offset: A0h set register

A4h clear register [returns the contents of the isochronous receive interrupt event

Default: 0000 000Xh

Table 4−18. Isochronous Receive Interrupt Event Register Description

BIT FIELD NAME TYPE DESCRIPTION

31−4 RSVD R Reserved. Bits 31−4 return 0s when read.

3 isoRecv3 RSC Isochronous receive channel 3 caused the interrupt event register bit 7 (isochRx) interrupt.

2 isoRecv2 RSC Isochronous receive channel 2 caused the interrupt event register bit 7 (isochRx) interrupt.

1 isoRecv1 RSC Isochronous receive channel 1 caused the interrupt event register bit 7 (isochRx) interrupt.

0 isoRecv0 RSC Isochronous receive channel 0 caused the interrupt event register bit 7 (isochRx) interrupt.

4−25

4.26 Isochronous Receive Interrupt Mask Register

The isochronous receive interrupt mask set/clear register enables the isochRx interrupt source on a per-channel

basis. Reads from either the set register or the clear register always return the contents of the isochronous receive

interrupt mask register. In all cases, the enables for each interrupt event align with the event register bits detailed in

Table 4−18.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Isochronous receive interrupt mask

Type R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Isochronous receive interrupt mask

Type R R R R R R R R R R R R RSC RSC RSC RSC

Default 0 0 0 0 0 0 0 0 0 0 0 0 X X X X

Type: Read/Set/Clear, Read-only

Offset: A8h set register

ACh clear register

Default: 0000 000Xh

4.27 Fairness Control Register

The fairness control register provides a mechanism by which software can direct the host controller to transmit

multiple asynchronous requests during a fairness interval. See Table 4−19 for a complete description of the register

contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Fairness control

Type R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Fairness control

Type R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Type: Read-only, Read/Write

Offset: DCh

Default: 0000 0000h

Table 4−19. Fairness Control Register Description

BIT FIELD NAME TYPE DESCRIPTION

31−8 RSVD R Reserved. Bits 31−8 return 0s when read.

7−0 pri_req R/W This field specifies the maximum number of priority arbitration requests for asynchronous request

packets that the link is permitted to make of the PHY device during a fairness interval.

4−26

4.28 Link Control Register

The link control set/clear register provides the control flags that enable and configure the link core protocol portions

of the TSB12LV26 device. It contains controls for the receiver and cycle timer. See Table 4−20 for a complete

description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Link control

Type R R R R R R R R R RSC RSCU RSC R R R R

Default 0 0 0 0 0 0 0 0 0 X X X 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Link control

Type R R R R R RSC RSC R R R R R R R R R

Default 0 0 0 0 0 X X 0 0 0 0 0 0 0 0 0

Type: Read/Set/Clear/Update, Read/Set/Clear, Read-only

Offset: E0h set register

E4h clear register

Default: 00X0 0X00h

Table 4−20. Link Control Register Description

BIT FIELD NAME TYPE DESCRIPTION

31−23 RSVD R Reserved. Bits 31−23 return 0s when read.

22 cycleSource RSC When bit 22 is set to 1, the cycle timer uses an external source (CYCLEIN) to determine when to roll

over the cycle timer. When this bit is cleared, the cycle timer rolls over when the timer reaches

3072 cycles of the 24.576-MHz clock (125 µs).

21 cycleMaster RSCU When bit 21 is set to 1 and the PHY device has notified the TSB12LV26 device that the PHY device

is root, the TSB12LV26 device generates a cycle start packet every time the cycle timer rolls over,

based on the setting of bit 22 (cycleSource). When bit 21 is cleared, the OHCI-Lynxt accepts

received cycle start packets to maintain synchronization with the node that is sending them. Bit 21

is automatically cleared when bit 25 (cycleTooLong) in the interrupt event register at OHCI offset

80h/84h (see Section 4.21, Interrupt Event Register) is set to 1. Bit 21 cannot be set to 1 until bit 25

(cycleTooLong) is cleared.

20 CycleTimerEnable RSC When bit 20 is set to 1, the cycle timer offset counts cycles of the 24.576-MHz clock and rolls over

at the appropriate time, based on the settings of the above bits. When this bit is cleared, the cycle

timer offset does not count.

19−11 RSVD R Reserved. Bits 19−11 return 0s when read.

10 RcvPhyPkt RSC When bit 10 is set to 1, the receiver accepts incoming PHY packets into the AR request context if

the AR request context is enabled. This bit does not control receipt of self-ID packets.

9 RcvSelfID RSC When bit 9 is set to 1, the receiver accepts incoming self-ID packets. Before setting this bit to 1,

software must ensure that the self-ID buffer pointer register contains a valid address.

8−0 RSVD R Reserved. Bits 8−0 return 0s when read.

Part #	TSB12LV26TPZEP
Description	V62/03627-01XE -OHCI-LYNX PCI-BASED - Trays
Category	IC
Availability	In Stock
Qty	2

TSB12LV26TPZEP

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