4−21

Table 4−16. Interrupt Mask Register Description (Continued)

BIT FIELD NAME TYPE DESCRIPTION

19 phy RSC When this bit and bit 19 (phy) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21,

Interrupt Event Register) are set to 1, this PHY-status-transfer interrupt mask enables interrupt

generation.

18 RSVD R Reserved. Bit 18 returns 0 when read.

17 busReset RSC When this bit and bit 17 (busReset) in the interrupt event register at OHCI offset 80h/84h (see

Section 4.21, Interrupt Event Register) are set to 1, this bus-reset interrupt mask enables interrupt

generation.

16 selfIDcomplete RSC When this bit and bit 16 (selfIDcomplete) in the interrupt event register at OHCI offset 80h/84h (see

Section 4.21, Interrupt Event Register) are set to 1, this self-ID-complete interrupt mask enables

interrupt generation.

15−10 RSVD R Reserved. Bits 15−10 return 0s when read.

9 lockRespErr RSC When this bit and bit 9 (lockRespErr) in the interrupt event register at OHCI offset 80h/84h (see

Section 4.21, Interrupt Event Register) are set to 1, this lock-response-error interrupt mask enables

interrupt generation.

8 postedWriteErr RSC When this bit and bit 8 (postedWriteErr) in the interrupt event register at OHCI offset 80h/84h (see

Section 4.21, Interrupt Event Register) are set to 1, this posted-write-error interrupt mask enables

interrupt generation.

7 isochRx RSC When this bit and bit 7 (isochRx) in the interrupt event register at OHCI offset 80h/84h (see

Section 4.21, Interrupt Event Register) are set to 1, this isochronous-receive-DMA interrupt mask

enables interrupt generation.

6 isochTx RSC When this bit and bit 6 (isochTx) in the interrupt event register at OHCI offset 80h/84h (see

Section 4.21, Interrupt Event Register) are set to 1, this isochronous-transmit-DMA interrupt mask

enables interrupt generation.

5 RSPkt RSC When this bit and bit 5 (RSPkt) in the interrupt event register at OHCI offset 80h/84h (see

Section 4.21, Interrupt Event Register) are set to 1, this receive-response-packet interrupt mask

enables interrupt generation.

4 RQPkt RSC When this bit and bit 4 (RQPkt) in the interrupt event register at OHCI offset 80h/84h (see

Section 4.21, Interrupt Event Register) are set to 1, this receive-request-packet interrupt mask

enables interrupt generation.

3 ARRS RSC When this bit and bit 3 (ARRS) in the interrupt event register at OHCI offset 80h/84h (see

Section 4.21, Interrupt Event Register) are set to 1, this asynchronous-receive-response-DMA

interrupt mask enables interrupt generation.

2 ARRQ RSC When this bit and bit 2 (ARRQ) in the interrupt event register at OHCI offset 80h/84h (see

Section 4.21, Interrupt Event Register) are set to 1, this asynchronous-receive-request-DMA

interrupt mask enables interrupt generation.

1 respTxComplete RSC When this bit and bit 1 (respTxComplete) in the interrupt event register at OHCI offset 80h/84h (see

Section 4.21, Interrupt Event Register) are set to 1, this response-transmit-complete interrupt mask

enables interrupt generation.

0 reqTxComplete RSC When this bit and bit 0 (reqTxComplete) in the interrupt event register at OHCI offset 80h/84h (see

Section 4.21, Interrupt Event Register) are set to 1, this request-transmit-complete interrupt mask

enables interrupt generation.

4−22

4.23 Isochronous Transmit Interrupt Event Register

The isochronous transmit interrupt event set/clear register reflects the interrupt state of the isochronous transmit

contexts. An interrupt is generated on behalf of an isochronous transmit context if an OUTPUT_LAST* command

completes and its interrupt bits are set to 1. Upon determining that the isochTx (bit 6) interrupt in the interrupt event

corresponding interrupt signal, or by writing a 1 in the corresponding bit in the set register. The only mechanism to

clear a bit in this register is to write a 1 to the corresponding bit in the clear register. See Table 4−17 for a complete

description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Isochronous transmit interrupt event

Type R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Isochronous transmit interrupt event

Type R R R R R R R R RSC RSC RSC RSC RSC RSC RSC RSC

Default 0 0 0 0 0 0 0 0 X X X X X X X X

Type: Read/Set/Clear, Read-only

Offset: 90h set register

94h clear register [returns the contents of the isochronous transmit interrupt event

when read]

Default: 0000 00XXh

Table 4−17. Isochronous Transmit Interrupt Event Register Description

BIT FIELD NAME TYPE DESCRIPTION

31−8 RSVD R Reserved. Bits 31−8 return 0s when read.

7 isoXmit7 RSC Isochronous transmit channel 7 caused the interrupt event register bit 6 (isochTx) interrupt.

6 isoXmit6 RSC Isochronous transmit channel 6 caused the interrupt event register bit 6 (isochTx) interrupt.

5 isoXmit5 RSC Isochronous transmit channel 5 caused the interrupt event register bit 6 (isochTx) interrupt.

4 isoXmit4 RSC Isochronous transmit channel 4 caused the interrupt event register bit 6 (isochTx) interrupt.

3 isoXmit3 RSC Isochronous transmit channel 3 caused the interrupt event register bit 6 (isochTx) interrupt.

2 isoXmit2 RSC Isochronous transmit channel 2 caused the interrupt event register bit 6 (isochTx) interrupt.

1 isoXmit1 RSC Isochronous transmit channel 1 caused the interrupt event register bit 6 (isochTx) interrupt.

0 isoXmit0 RSC Isochronous transmit channel 0 caused the interrupt event register bit 6 (isochTx) interrupt.

4−23

4.24 Isochronous Transmit Interrupt Mask Register

The isochronous transmit interrupt mask set/clear register enables the isochTx interrupt source on a per-channel

basis. Reads from either the set register or the clear register always return the contents of the isochronous transmit

interrupt mask register. In all cases, the enables for each interrupt event align with the isochronous transmit interrupt

event register bits detailed in Table 4−17.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Isochronous transmit interrupt mask

Type R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Isochronous transmit interrupt mask

Type R R R R R R R R RSC RSC RSC RSC RSC RSC RSC RSC

Default 0 0 0 0 0 0 0 0 X X X X X X X X

Type: Read/Set/Clear, Read-only

Offset: 98h set register

9Ch clear register

Default: 0000 00XXh

Part #	TSB12LV26TPZEP
Description	V62/03627-01XE -OHCI-LYNX PCI-BASED - Trays
Category	IC
Availability	In Stock
Qty	2

TSB12LV26TPZEP

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