4−15

4.18 Self-ID Count Register

The self-ID count register keeps a count of the number of times the bus self-ID process has occurred, flags self-ID

packet errors, and keeps a count of the self-ID data in the self-ID buffer. See Table 4−12 for a complete description

of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Self-ID count

Type RU R R R R R R R RU RU RU RU RU RU RU RU

Default X 0 0 0 0 0 0 0 X X X X X X X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Self-ID count

Type R R R R R RU RU RU RU RU RU RU RU RU R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Type: Read/Update, Read-only

Offset: 68h

Default: X0XX 0000h

Table 4−12. Self-ID Count Register Description

BIT FIELD NAME TYPE DESCRIPTION

31 selfIDError RU When bit 31 is set to 1, an error was detected during the most recent self-ID packet reception. The

contents of the self-ID buffer are undefined. This bit is cleared after a self-ID reception in which no

errors are detected. Note that an error can be a hardware error or a host bus write error.

30−24 RSVD R Reserved. Bits 30−24 return 0s when read.

23−16 selfIDGeneration RU The value in this field increments each time a bus reset is detected. This field rolls over to 0 after

reaching 255.

15−11 RSVD R Reserved. Bits 15−11 return 0s when read.

10−2 selfIDSize RU This field indicates the number of quadlets that have been written into the self-ID buffer for the current

bits 23−16 (selfIDGeneration field). This includes the header quadlet and the self-ID data. This field

is cleared to 0 when the self-ID reception begins.

1−0 RSVD R Reserved. Bits 1 and 0 return 0s when read.

4−16

4.19 Isochronous Receive Channel Mask High Register

The isochronous receive channel mask high set/clear register enables packet receives from the upper 32

isochronous data channels. A read from either the set register or clear register returns the content of the isochronous

receive channel mask high register. See Table 4−13 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Isochronous receive channel mask high

Type RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC

Default X X X X X X X X X X X X X X X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Isochronous receive channel mask high

Type RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC

Default X X X X X X X X X X X X X X X X

Type: Read/Set/Clear

Offset: 70h set register

74h clear register

Default: XXXX XXXXh

Table 4−13. Isochronous Receive Channel Mask High Register Description

BIT FIELD NAME TYPE DESCRIPTION

31 isoChannel63 RSC When bit 31 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 63.

30 isoChannel62 RSC When bit 30 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 62.

29 isoChannel61 RSC When bit 29 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 61.

28 isoChannel60 RSC When bit 28 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 60.

27 isoChannel59 RSC When bit 27 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 59.

26 isoChannel58 RSC When bit 26 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 58.

25 isoChannel57 RSC When bit 25 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 57.

24 isoChannel56 RSC When bit 24 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 56.

23 isoChannel55 RSC When bit 23 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 55.

22 isoChannel54 RSC When bit 22 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 54.

21 isoChannel53 RSC When bit 21 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 53.

20 isoChannel52 RSC When bit 20 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 52.

19 isoChannel51 RSC When bit 19 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 51.

18 isoChannel50 RSC When bit 18 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 50.

17 isoChannel49 RSC When bit 17 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 49.

16 isoChannel48 RSC When bit 16 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 48.

15 isoChannel47 RSC When bit 15 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 47.

14 isoChannel46 RSC When bit 14 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 46.

13 isoChannel45 RSC When bit 13 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 45.

12 isoChannel44 RSC When bit 12 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 44.

11 isoChannel43 RSC When bit 11 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 43.

10 isoChannel42 RSC When bit 10 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 42.

9 isoChannel41 RSC When bit 9 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 41.

8 isoChannel40 RSC When bit 8 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 40.

7 isoChannel39 RSC When bit 7 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 39.

4−17

Table 4−13. Isochronous Receive Channel Mask High Register Description (Continued)

BIT FIELD NAME TYPE DESCRIPTION

6 isoChannel38 RSC When bit 6 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 38.

5 isoChannel37 RSC When bit 5 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 37.

4 isoChannel36 RSC When bit 4 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 36.

3 isoChannel35 RSC When bit 3 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 35.

2 isoChannel34 RSC When bit 2 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 34.

1 isoChannel33 RSC When bit 1 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 33.

0 isoChannel32 RSC When bit 0 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 32.

4.20 Isochronous Receive Channel Mask Low Register

The isochronous receive channel mask low set/clear register enables packet receives from the lower 32 isochronous

data channels. See Table 4−14 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Isochronous receive channel mask low

Type RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC

Default X X X X X X X X X X X X X X X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Isochronous receive channel mask low

Type RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC

Default X X X X X X X X X X X X X X X X

Type: Read/Set/Clear

Offset: 78h set register

7Ch clear register

Default: XXXX XXXXh

Table 4−14. Isochronous Receive Channel Mask Low Register Description

BIT FIELD NAME TYPE DESCRIPTION

31 isoChannel31 RSC When bit 31 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 31.

30 isoChannel30 RSC When bit 30 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 30.

29−2 isoChanneln RSC Bits 29 through 2 (isoChanneln, where n = 29, 28, 27, …, 2) follow the same pattern as bits 31 and 30.

1 isoChannel1 RSC When bit 1 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 1.

0 isoChannel0 RSC When bit 0 is set to 1, the TSB12LV26 device is enabled to receive from isochronous channel number 0.

Part #	TSB12LV26TPZEP
Description	V62/03627-01XE -OHCI-LYNX PCI-BASED - Trays
Category	IC
Availability	In Stock
Qty	2

TSB12LV26TPZEP

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