4−13
4.16 Host Controller Control Register
The host controller control set/clear register pair provides flags for controlling the TSB12LV26 device. See Table 4−11
for a complete description of the register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Host controller control
Type R RSC R R R R R R RC RSC R R RSC RSC RSC RSCU
Default 0 X 0 0 0 0 0 0 0 0 0 0 0 X 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Host controller control
Type R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Host controller control
Type: Read/Set/Clear/Update, Read/Set/Clear, Read/Clear, Read-only
Offset: 50h set register
54h clear register
Default: X00X 0000h
Table 4−11. Host Controller Control Register Description
BIT FIELD NAME TYPE DESCRIPTION
31 RSVD R Reserved. Bit 31 returns 0 when read.
30 noByteSwapData RSC Bit 30 controls whether physical accesses to locations outside the TSB12LV26 device itself, as
well as any other DMA data accesses, are swapped.
29−24 RSVD R Reserved. Bits 29−24 return 0s when read.
23 programPhyEnable RC Bit 23 informs upper-level software that lower-level software has consistently configured the IEEE
1394a-2000 enhancements in the link and PHY devices. When this bit is set to 1, generic software
such as the OHCI driver is responsible for configuring IEEE 1394a-2000 enhancements in the
PHY device and bit 22 (aPhyEnhanceEnable) in the TSB12LV26 device. When this bit is cleared
to 0, the generic software may not modify the IEEE 1394a-2000 enhancements in the TSB12LV26
or PHY device and cannot interpret the setting of bit 22 (aPhyEnhanceEnable). This bit is
initialized from serial EEPROM.
22 aPhyEnhanceEnable RSC When bits 23 (programPhyEnable) and 17 (linkEnable) are 1, the OHCI driver can set bit 22 to
1 to use all IEEE 1394a-2000 enhancements. When bit 23 (programPhyEnable) is cleared to 0,
the software does not change PHY enhancements or this bit.
21−20 RSVD R Reserved. Bits 21 and 20 return 0s when read.
19 LPS RSC Bit 19 controls the link power status. Software must set this bit to 1 to permit link-PHY
communication. A 0 prevents link-PHY communication.
The OHCI-link is divided into two clock domains (PCI_CLK and PHY_SCLK). If software tries to
access any register in the PHY_SCLK domain while the PHY_SCLK is disabled, a target abort
is issued by the link. This problem can be avoided by setting bit 4 (DIS_TGT_ABT) to 1 in the
miscellaneous configuration register at offset F0h in the PCI configuration space (see
Section 3.20, Miscellaneous Configuration Register). This allows the link to respond to these
types of requests by returning all Fs (hex). It is recommended that this bit be set to 1 and is
programmable via the ROM or BIOS.
OHCI registers at offsets DCh−F0h and 100h−11Ch are in the PHY_SCLK domain.
After setting LPS software must wait approximately 10 ms before attempting to access any of the
OHCI registers. This gives the PHY_SCLK time to stabilize.
18 postedWriteEnable RSC Bit 18 enables (1) or disables (0) posted writes. Software must change this bit only when bit 17
(linkEnable) is 0.
