4−6

4.3 Asynchronous Transmit Retries Register

The asynchronous transmit retries register indicates the number of times the TSB12LV26 device attempts a retry for

asynchronous DMA request transmit and for asynchronous physical and DMA response transmit. See Table 4−4 for

a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Asynchronous transmit retries

Type R R R R R R R R R R R R R R R R

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Asynchronous transmit retries

Type R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Type: Read/Write, Read-only

Offset: 08h

Default: 0000 0000h

Table 4−4. Asynchronous Transmit Retries Register Description

BIT FIELD NAME TYPE DESCRIPTION

31−29 secondLimit R The second limit field returns 0s when read, because outbound dual-phase retry is not

implemented.

28−16 cycleLimit R The cycle limit field returns 0s when read, because outbound dual-phase retry is not implemented.

15−12 RSVD R Reserved. Bits 15−12 return 0s when read.

11−8 maxPhysRespRetries R/W The maxPhysRespRetries field tells the physical response unit how many times to attempt to retry

the transmit operation for the response packet when a busy acknowledge or ack_data_error is

received from the target node.

7−4 maxATRespRetries R/W The maxATRespRetries field tells the asynchronous transmit response unit how many times to

attempt to retry the transmit operation for the response packet when a busy acknowledge or

ack_data_error is received from the target node.

3−0 maxATReqRetries R/W The maxATReqRetries field tells the asynchronous transmit DMA request unit how many times

to attempt to retry the transmit operation for the response packet when a busy acknowledge or

ack_data_error is received from the target node.

4.4 CSR Data Register

The CSR data register accesses the bus-management CSR registers from the host through compare-swap

operations. This register contains the data to be stored in a CSR if the compare is successful.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name CSR data

Type R R R R R R R R R R R R R R R R

Default X X X X X X X X X X X X X X X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name CSR data

Type R R R R R R R R R R R R R R R R

Default X X X X X X X X X X X X X X X X

Type: Read-only

Offset: 0Ch

Default: XXXX XXXXh

4−7

4.5 CSR Compare Register

The CSR compare register accesses the bus-management CSR registers from the host through compare-swap

operations. This register contains the data to be compared with the existing value of the CSR resource.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name CSR compare

Type R R R R R R R R R R R R R R R R

Default X X X X X X X X X X X X X X X X

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name CSR compare

Type R R R R R R R R R R R R R R R R

Default X X X X X X X X X X X X X X X X

Type: Read-only

Offset: 10h

Default: XXXX XXXXh

4.6 CSR Control Register

The CSR control register accesses the bus-management CSR registers from the host through compare-swap

operations. This register controls the compare-swap operation and selects the CSR resource. See Table 4−5 for a

complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name CSR control

Type RU R R R R R R R R R R R R R R R

Default 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name CSR control

Type R R R R R R R R R R R R R R R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X

Type: Read/Write, Read/Update, Read-only

Offset: 14h

Default: 8000 000Xh

Table 4−5. CSR Control Register Description

BIT FIELD NAME TYPE DESCRIPTION

31 csrDone RU Bit 31 is set to 1 by the TSB12LV26 device when a compare-swap operation is complete. It is cleared

whenever this register is written.

30−2 RSVD R Reserved. Bits 30−2 return 0s when read.

1−0 csrSel R/W This field selects the CSR resource as follows:

00 = BUS_MANAGER_ID

01 = BANDWIDTH_AVAILABLE

10 = CHANNELS_AVAILABLE_HI

11 = CHANNELS_AVAILABLE_LO

4−8

4.7 Configuration ROM Header Register

The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offset

FFFF F000 0400h. See Table 4−6 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Configuration ROM header

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Configuration ROM header

Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Default X X X X X X X X X X X X X X X X

Type: Read/Write

Offset: 18h

Default: 0000 XXXXh

Table 4−6. Configuration ROM Header Register Description

BIT FIELD NAME TYPE DESCRIPTION

31−24 info_length R/W IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control

23−16 crc_length R/W IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control

15−0 rom_crc_value R/W IEEE 1394 bus-management field. Must be valid at any time bit 17 (linkEnable) in the host controller

control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to

1. The reset value is undefined if no serial EEPROM is present. If a serial EEPROM is present, this

field is loaded from the serial EEPROM.

4.8 Bus Identification Register

The bus identification register externally maps to the first quadlet in the Bus_Info_Block and contains the constant

3133 3934h, which is the ASCII value of 1394.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Bus identification

Type R R R R R R R R R R R R R R R R

Default 0 0 1 1 0 0 0 1 0 0 1 1 0 0 1 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Bus identification

Type R R R R R R R R R R R R R R R R

Default 0 0 1 1 1 0 0 1 0 0 1 1 0 1 0 0

Type: Read-only

Offset: 1Ch

Default: 3133 3934h

Part #	TSB12LV26TPZEP
Description	V62/03627-01XE -OHCI-LYNX PCI-BASED - Trays
Category	IC
Availability	In Stock
Qty	2

TSB12LV26TPZEP

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