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TSB12LV26TPZEP

Part # TSB12LV26TPZEP
Description V62/03627-01XE -OHCI-LYNX PCI-BASED - Trays
Category IC
Availability In Stock
Qty 2
Qty Price
1 + $10.15828
Manufacturer Available Qty
Texas Instruments
Date Code: 0336
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

4−3
Table 4−1. OHCI Register Map (Continued)
DMA CONTEXT REGISTER NAME ABBREVIATION OFFSET
Asynchronous context control
ContextControlSet 180h
Asychronous
Asynchronous context control
ContextControlClear 184h
Asychronous
Request Transmit
Reserved 188h
Request Transmit
[ ATRQ ]
Asynchronous context command pointer CommandPtr 18Ch
[ ATRQ ]
Reserved 190h−19Ch
Asynchronous context control
ContextControlSet 1A0h
Asychronous
Asynchronous context control
ContextControlClear 1A4h
Asychronous
Response Transm
it
Reserved 1A8h
Response Transmit
[ ATRS ]
Asynchronous context command pointer CommandPtr 1ACh
[ ATRS ]
Reserved 1B0h−1BCh
Asynchronous context control
ContextControlSet 1C0h
Asychronous
Asynchronous context control
ContextControlClear 1C4h
Asychronous
Request Receive
Reserved 1C8h
Request Receive
[ ARRQ ]
Asynchronous context command pointer CommandPtr 1CCh
[ ARRQ ]
Reserved 1D0h−1DCh
Asynchronous context control
ContextControlSet 1E0h
Asychronous
Asynchronous context control
ContextControlClear 1E4h
Asychronous
Response Receive
Reserved 1E8h
Response Receive
[ ARRS ]
Asynchronous context command pointer CommandPtr 1ECh
[ ARRS ]
Reserved 1F0h−1FCh
Isochronous transmit context control
ContextControlSet 200h + 16*n
Isochronous
Isochronous transmit context control
ContextControlClear 204h + 16*n
Isochronous
Transmit Context n
Reserved 208h + 16*n
Transmit Context n
n = 0, 1, 2, 3, , 7
Isochronous transmit context command
pointer
CommandPtr 20Ch + 16*n
Reserved 280h−3FCh
Isochronous receive context control
ContextControlSet 400h + 32*n
Isochronous
Isochronous receive context control
ContextControlClear 404h + 32*n
Isochronous
Receive Context n
Reserved 408h + 32*n
Receive Context n
n = 0, 1, 2, 3
Isochronous receive context command
pointer
CommandPtr 40Ch + 32*n
Context match ContextMatch 410h + 32*n
4−4
4.1 OHCI Version Register
The OHCI version register indicates the OHCI version support and whether or not the serial EEPROM is present. See
Table 4−2 for a complete description of the register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name OHCI version
Type R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 0 0 X 0 0 0 0 0 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name OHCI version
Type R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: OHCI version
Type: Read-only
Offset: 00h
Default: 0X01 0000h
Table 4−2. OHCI Version Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−25 RSVD R Reserved. Bits 31−25 return 0s when read.
24 GUID_ROM R The TSB12LV26 device sets bit 24 to 1 if the serial EEPROM is detected. If the serial EEPROM is
present, the Bus_Info_Block is automatically loaded on system (hardware) reset.
23−16 version R Major version of the OHCI. The TSB12LV26 device is compliant with the 1394 Open Host Controller
Interface Specification; thus, this field reads 01h.
15−8 RSVD R Reserved. Bits 15−8 return 0s when read.
7−0 revision R Minor version of the OHCI. The TSB12LV26 device is compliant with the 1394 Open Host Controller
Interface Specification; thus, this field reads 00h.
4−5
4.2 GUID ROM Register
The GUID ROM register accesses the serial EEPROM and is applicable only if bit 24 (GUID_ROM) in the OHCI
version register at OHCI offset 00h (see Section 4.1, OHCI Version Register) is set to 1. See Table 4−3 for a complete
description of the register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name GUID ROM
Type RSU R R R R R RSU R RU RU RU RU RU RU RU RU
Default 0 0 0 0 0 0 0 0 X X X X X X X X
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name GUID ROM
Type R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: GUID ROM
Type: Read/Set/Update, Read/Update, Read-only
Offset: 04h
Default: 00XX 0000h
Table 4−3. GUID ROM Register Description
BIT FIELD NAME TYPE DESCRIPTION
31 addrReset RSU Software sets bit 31 to 1 to reset the GUID ROM address to 0. When the TSB12LV26 device completes
the reset, it clears this bit. The TSB12LV26 device does not automatically fill bits 23−16 (rdData field)
with the 0
th
byte.
30−26 RSVD R Reserved. Bits 30−26 return 0s when read.
25 rdStart RSU A read of the currently addressed byte is started when bit 25 is set to 1. This bit is automatically cleared
when the TSB12LV26 device completes the read of the currently addressed GUID ROM byte.
24 RSVD R Reserved. Bit 24 returns 0 when read.
23−16 rdData RU This field contains the data read from the GUID ROM.
15−0 RSVD R Reserved. Bits 15−0 return 0s when read.
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