7.4 Switching Characteristics for PCI Interface 7−3. . . . . . . . . . . . . . . . . . . . . .

7.5 Switching Characteristics for PHY-Link Interface 7−3. . . . . . . . . . . . . . . . .

8 Mechanical Information 8−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Illustrations

Figure Title Page

2−1 Terminal Assignments 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−1 TSB12LV26 Block Diagram 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−1 GPIO2 and GPIO3 Logic Diagram 5−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Tables

Table Title Page

2−1 Signals Sorted by Terminal Number 2−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−2 Signal Names Sorted Alphanumerically to Terminal Number 2−3. . . . . . . . . .

2−3 Power Supply Terminals 2−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−4 PCI System Terminals 2−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−5 PCI Address and Data Terminals 2−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−6 PCI Interface Control Terminals 2−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−7 IEEE 1394 PHY/Link Terminals 2−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−8 Miscellaneous Terminals 2−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−1 Bit Field Access Tag Descriptions 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−2 PCI Configuration Register Map 3−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−3 Command Register Description 3−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−4 Status Register Description 3−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−5 Class Code and Revision ID Register Description 3−6. . . . . . . . . . . . . . . . . . .

3−6 Latency Timer and Class Cache Line Size Register Description 3−6. . . . . . .

3−7 Header Type and BIST Register Description 3−7. . . . . . . . . . . . . . . . . . . . . . . .

3−8 OHCI Base Address Register Description 3−7. . . . . . . . . . . . . . . . . . . . . . . . . .

3−9 Subsystem Identification Register Description 3−8. . . . . . . . . . . . . . . . . . . . . .

3−10 Interrupt Line and Pin Register Description 3−9. . . . . . . . . . . . . . . . . . . . . . . . .

3−11 MIN_GNT and MAX_LAT Register Description 3−10. . . . . . . . . . . . . . . . . . . . .

3−12 OHCI Control Register Description 3−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−13 Capability ID and Next Item Pointer Register Description 3−11. . . . . . . . . . . . .

3−14 Power Management Capabilities Register Description 3−12. . . . . . . . . . . . . . .

3−15 Power Management Control and Status Register Description 3−13. . . . . . . . .

3−16 Power Management Extension Register Description 3−14. . . . . . . . . . . . . . . . .

3−17 Miscellaneous Configuration Register 3−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−18 Link Enhancement Control Register Description 3−16. . . . . . . . . . . . . . . . . . . .

3−19 Subsystem Access Register Description 3−17. . . . . . . . . . . . . . . . . . . . . . . . . . .

3−20 GPIO Control Register Description 3−18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−1 OHCI Register Map 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−2 OHCI Version Register Description 4−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−3 GUID ROM Register Description 4−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−4 Asynchronous Transmit Retries Register Description 4−6. . . . . . . . . . . . . . . .

4−5 CSR Control Register Description 4−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−6 Configuration ROM Header Register Description 4−8. . . . . . . . . . . . . . . . . . . .

4−7 Bus Options Register Description 4−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−8 Configuration ROM Mapping Register Description 4−11. . . . . . . . . . . . . . . . . . .

4−9 Posted Write Address Low Register Description 4−11. . . . . . . . . . . . . . . . . . . .

4−10 Posted Write Address High Register Description 4−12. . . . . . . . . . . . . . . . . . . .

4−11 Host Controller Control Register Description 4−13. . . . . . . . . . . . . . . . . . . . . . . .

4−12 Self-ID Count Register Description 4−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−13 Isochronous Receive Channel Mask High Register Description 4−16. . . . . . .

4−14 Isochronous Receive Channel Mask Low Register Description 4−17. . . . . . . .

4−15 Interrupt Event Register Description 4−18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−16 Interrupt Mask Register Description 4−20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−17 Isochronous Transmit Interrupt Event Register Description 4−22. . . . . . . . . . .

4−18 Isochronous Receive Interrupt Event Register Description 4−24. . . . . . . . . . .

4−19 Fairness Control Register Description 4−25. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−20 Link Control Register Description 4−26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−21 Node Identification Register Description 4−27. . . . . . . . . . . . . . . . . . . . . . . . . . .

4−22 PHY Control Register Description 4−28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−23 Isochronous Cycle Timer Register Description 4−29. . . . . . . . . . . . . . . . . . . . . .

4−24 Asynchronous Request Filter High Register Description 4−30. . . . . . . . . . . . .

4−25 Asynchronous Request Filter Low Register Description 4−32. . . . . . . . . . . . . .

4−26 Physical Request Filter High Register Description 4−33. . . . . . . . . . . . . . . . . . .

4−27 Physical Request Filter Low Register Description 4−35. . . . . . . . . . . . . . . . . . .

4−28 Asynchronous Context Control Register Description 4−36. . . . . . . . . . . . . . . . .

4−29 Asynchronous Context Command Pointer Register Description 4−37. . . . . . .

4−30 Isochronous Transmit Context Control Register Description 4−38. . . . . . . . . .

4−31 Isochronous Receive Context Control Register Description 4−39. . . . . . . . . . .

4−32 Isochronous Receive Context Match Register Description 4−42. . . . . . . . . . . .

6−1 Registers and Bits Loadable Through Serial ROM 6−1. . . . . . . . . . . . . . . . . . .

6−2 Serial ROM Map 6−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−1

1 Introduction

1.1 Description

The Texas Instruments TSB12LV26 device is a PCI-to-1394 host controller compliant with the PCI Local Bus

Specification, PCI Bus Power Management Interface Specification, IEEE Std 1394-1995, and 1394 Open Host

Controller Interface Specification. The chip provides the IEEE 1394 link function and is compatible with 100M bits/s,

200M bits/s, and 400M bits/s serial bus data rates.

As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a-2000, internal

control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through

configuration cycles specified by PCI and provides plug-and-play (PnP) compatibility. Furthermore, the TSB12LV26

device is compliant with the PCI Bus Power Management Interface Specification, per the PC 99 Design Guide

requirements. TSB12LV26 device supports the D0, D2, and D3 power states.

The TSB12LV26 design provides PCI bus master bursting and is capable of transferring a cacheline of data at

132M bytes/s after connection to the memory controller. Since PCI latency can be large, deep FIFOs are provided

to buffer 1394 data.

The TSB12LV26 device provides physical write posting buffers and a highly-tuned physical data path for SBP-2

performance. The TSB12LV26 device also provides multiple isochronous contexts, multiple cacheline burst

transfers, advanced internal arbitration, and bus-holding buffers on the PHY/link interface.

An advanced CMOS process achieves low power consumption and allows the TSB12LV26 device to operate at PCI

clock rates up to 33 MHz.

1.2 Features

The TSB12LV26-EP device supports the following features:

• Controlled Baseline

• One Assembly/Test Site, One Fabrication Site

• Extended Temperature Performance of −40°C to 110°C

• Enhanced Diminishing Manufacturing Sources (DMS) Support

• Enhanced Product Change Notification

• Qualification Pedigree

†

• 3.3-V and 5-V PCI bus signaling

• 3.3-V supply (core voltage is internally regulated to 1.8 V)

• Serial bus data rates of 100M bits/s, 200M bits/s, and 400M bits/s

• Physical write posting of up to three outstanding transactions

• Serial ROM interface supports 2-wire devices

• External cycle timer control for customized synchronization

• PCI burst transfers and deep FIFOs to tolerate large host latency

• Two general-purpose I/Os

• Fabricated in advanced low-power CMOS process

• Packaged in 100-terminal LQFP (PZ)

• PCI_CLKRUN

protocol

†

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range.

This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST,

electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this

component beyond specified performance and environmental limits.

Part #	TSB12LV26TPZEP
Description	V62/03627-01XE -OHCI-LYNX PCI-BASED - Trays
Category	IC
Availability	In Stock
Qty	2

TSB12LV26TPZEP

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