TPS767D301-EP
SGLS327A –FEBRUARY 2006–REVISED APRIL 2010
www.ti.com
APPLICATION INFORMATION
The features of the TPS767D301-EP (low-dropout voltage, ultra-low quiescent current, power-saving shutdown
mode, and a supply-voltage supervisor) and the power-dissipation properties of the TSSOP PowerPAD package
have enabled the integration of the dual LDO regulator with high output current for use in DSP and other
multiple-voltage applications.
Device Operation
The TPS767D301-EP features very low quiescent current, which remains virtually constant even with varying
loads. Conventional LDO regulators use a pnp pass element, the base current of which is directly proportional to
the load current through the regulator (I
B
= I
C
/b). Close examination of the data sheets reveals that these devices
typically are specified under near no-load conditions; actual operating currents are much higher, as evidenced by
typical quiescent current versus load current curves. The TPS767D301-EP uses a PMOS transistor to pass
current; because the gate of the PMOS is voltage driven, operating current is low and invariable over the full load
range. The TPS767D301-EP specifications reflect actual performance under load conditions.
Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into
dropout. The resulting drop in b forces an increase in I
B
to maintain the load. During power up, this translates to
large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems, it
means rapid battery discharge when the voltage decays below the minimum required for regulation.
The TPS767D301-EP quiescent current remains low, even when the regulator drops out, eliminating both
problems. The TPS767D301-EP also features a shutdown mode that places the output in the high-impedance
state (essentially equal to the feedback-divider resistance) and reduces quiescent current to under 2 mA. If the
shutdown feature is not used, EN should be tied to ground. Response to an enable transition is quick; regulated
output voltage typically is reestablished in 120 ms.
Minimum Load Requirements
The TPS767D301-EP is stable, even at zero load. No minimum load is required for operation.
FB – Pin Connection (Adjustable Version Only)
The FB pin is an input pin to sense the output voltage and close the loop for the adjustable option. The output
voltage is sensed through a resistor divider network to close the loop (see Figure 27). Normally, this connection
should be as short as possible; however, the connection can be made near a critical circuit to improve
performance at that point. Internally, FB connects to a high-impedance wide-bandwidth amplifier, and noise
pickup feeds through to the regulator output. Routing the FB connection to minimize/avoid noise pickup is
essential. In fixed-output options, this pin is a no connect.
External Capacitor Requirements
An input capacitor is not required; however, a ceramic bypass capacitor (0.047 pF to 0.1 mF) improves load
transient response and noise rejection when the TPS767D301-EP is located more than a few inches from the
power supply. A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load
transients with fast rise times are anticipated.
Like all low dropout regulators, the TPS767D301-EP requires an output capacitor connected between OUT and
GND to stabilize the internal control loop. The minimum recommended capacitance value is 10 mF and the
equivalent series resistance (ESR) must be between 60 mΩ and 1.5 Ω. Capacitor values of 10 mF or larger are
acceptable, provided the ESR is less than 1.5 Ω. Solid tantalum electrolytic, aluminum electrolytic, and multilayer
ceramic capacitors are all suitable, provided they meet the requirements previously described.
When it is necessary to achieve low height requirements along with high output current and/or high ceramic load
capacitance, several higher ESR capacitors can be used in parallel to meet the previous guidelines.
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