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TPS5430DDA

Part # TPS5430DDA
Description 5.5V -36V INPUT, 3-A STEP DOWN CONVERTER - Rail/Tube
Category IC
Availability Out of Stock
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

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L
MIN
V
OUT(MAX)
V
IN(MAX)
V
OUT
V
IN(max)
K
IND
I
OUT
F
SW
(4)
I
L(RMS)
I
2
OUT(MAX)
1
12
V
OUT
V
IN(MAX)
V
OUT
V
IN(MAX)
L
OUT
F
SW
0.8
2
(5)
I
L(PK)
I
OUT(MAX)
V
OUT
V
IN(MAX)
V
OUT
1.6 V
IN(MAX)
L
OUT
F
SW
(6)
f
CO
f
LC
2
85 V
OUT
(7)
TPS5430
SLVS632 JANUARY 2006
Output Filter Componts
Two components need to be selected for the output filter, L1 and C2. Since the TPS5430 is an internally
compensated device, a limited range of filter component types and values can be supported.
Inductor Selection
To calculate the minimum value of the output inductor, use Equation 4 :
K
IND
is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
Three things need to be considered when determining the amount of ripple current in the inductor: the peak to
peak ripple current affects the output ripple voltage amplitude, the ripple current affects the peak switch current
and the amount of ripple current determines at what point the circuit will become discontinuous. For designs
using the TPS5430, K
IND
of 0.2 to 0.3 yields good results. Low output ripple voltages can be obtained when
paired with the proper output capacitor, the peak switch current will be well below the current limit set point and
relatively low load currents can be sourced before dicontinuous operation.
For this design example use K
IND
= 0.2 and the minimum inductor value is calculated to be 12.5 µ H. The next
highest standard value is 15 µ H, which is used in this design.
For the output filter inductor it is important that the RMS current and saturation current ratings not be exceeded.
The RMS inductor current can be found from Equation 5 :
and the peak inductor current can be determined with Equation 6 :
For this design, the RMS inductor current is 3.003 A, and the peak inductor current is 3.31 A. The chosen
inductor is a Sumida CDRH104R-150 15 µ H. It has a saturation current rating of 3.4 A and a RMS current rating
of 3.6 A, easily meeting these requirements. A lesser rated inductor could be used, however this device was
chosen because of its low profile component height. In general, inductor values for use with the TPS5430 are in
the range of 10 µ H to 100 µ H.
Capacitor Selection
The important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalent
series resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is important
because along with the inductor ripple current it determines the amount of output ripple voltage. The actual value
of the output capacitor is not critical, but some practical limits do exist. Consider the relationship between the
desired closed loop crossover frequency of the design and LC corner frequency of the output filter. Due to the
design of the internal compensation, it is desirable to keep the closed loop crossover frequency in the range 3
kHz to 30 kHz as this frequency range has adequate phase boost to allow for stable operation. For this design
example, it is assumed that the intended closed loop crossover frequency will be between 2590 Hz and 24 kHz
and also below the ESR zero of the output capacitor. Under these conditions the closed loop crossover
frequency will be related to the LC corner frequency by:
And the desired output capacitor value for the output filter to:
13
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C
OUT
1
3357 L
OUT
f
CO
V
OUT
(8)
ESR
MAX
1
2 C
OUT
f
CO
(9)
V
p
p(MAX)
ESR
MAX
V
OUT
V
IN(MAX)
V
OUT
N
C
V
IN(MAX)
L
OUT
F
SW
(10)
I
COUT(RMS)
1
12
V
OUT
V
IN(MAX)
V
OUT
V
IN(MAX)
L
OUT
F
SW
N
C
(11)
R2
R1 1.221
V
OUT
1.221
(12)
TPS5430
SLVS632 JANUARY 2006
For a desired crossover of 18 kHz and a 15- µ H inductor, the calculated value for the output capacitor is 220 µ F.
The capacitor type shold be chosen so that the ESR zero is above the loop crossover. The maximum ESR
should be: (Add new equation)
The maximum ESR of the output capacitor also determines the amount of output ripple as specified in the initial
design parameters. The output ripple voltage is the inductor ripple current times the ESR of the output filter.
Check that the maximum specified ESR as listed in the capacitor data sheet will result in an acceptable output
ripple voltage:
Where:
V
P-P
is the desired peak-to-peak output ripple.
N
C
is the number of parallel output capacitors.
F
SW
is the switching frequency.
For this design example, a single 220- µ F output capacitor is chosen for C3. The calculated RMS ripple current is
143 mA and the maximum ESR required is 40 m . A capacitor that meets these requirements is a Sanyo
Poscap 10TPB220M, rated at 10 V with a maximum ESR of 40 m and a ripple current rating of 3.0 A. An
additional small 0.1- µ F ceramic bypass capacitor may also used, but is not included in this design.
The minimum ESR of the output capacitor should also be considered. For good phase margin, the ESR zero
when the ESR is at a minimum should not be too far above the internal compensation poles at 24 and 54 kHz.
The selected output capacitor must also be rated for a voltage greater than the desired output voltage plus one
half the ripple voltage. Any derating amount must also be included. The maximum RMS ripple current in the
output capacitor is given by Equation 11 :
Where:
N
C
is the number of output capacitors in parallel.
F
SW
is the switching frequency.
Other capacitor types can be used with the TPS5430, depending on the needs of the application.
Output Voltage Setpoint
The output voltage of the TPS5430 is set by a resistor divider (R1 and R2) from the output to the VSENSE pin.
Calculate the R2 resistor value for the output voltage of 5.0 V using Equation 12 :
For any TPS5430 design, start with an R1 value of 10 k . R2 is then 3.24 k .
Boot Capacitor
The boot capacitor should be 0.01 µ F.
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+
PwPd
6
9
4
2
3
GND
1235 V
ENA
NC
NC
L1
22 Hm
PH
EN
C1
10 Fm
VIN
5
7
1
8
5 V
VSNS
U1
TPS5430DDA
BOOT
C3
220 Fm
VIN
R2
3.24 kW
C2
0.01 Fm
VOUT
R1
10 kW
SBL845
D1
ADVANCED INFORMATION
Output Voltage Limitations
V
OUTMAX
0.87
V
INMIN
I
OMAX
0.230
V
D
I
OMAX
R
L
V
D
(13)
V
OUTMIN
0.12
V
INMAX
I
OMIN
0.110
V
D
I
OMIN
R
L
V
D
(14)
TPS5430
SLVS632 JANUARY 2006
Catch Diode
The TPS5430 is designed to operate using an external catch diode between PH and GND. The selected diode
must meet the absolute maximum ratings for the application: Reverse voltage must be higher than the maximum
voltage at the PH pin, which is VINMAX + 0.5 V. Peak current must be greater than IOUTMAX plus on half the
peak to peak inductor current. Forward voltage drop should be small for higher efficiencies. It is important to note
that the catch diode conduction time is typically longer than the high-side FET on time, so attention paid to diode
parameters can make a marked improvement in overall efficiency. Additionally, check that the device chosen is
capable of dissipating the power losses. For this design, a Diodes, Inc. B340A is chosen, with a reverse voltage
of 40 V, forward current of 3 A, and a forward voltage drop of 0.5V.
Additional Circuits
Figure 12 shows an application circuit utilizing a wide input voltage range. The design parameters are simillar to
those given for the design example, with a larger value output inductor and a lower closed loop crosover
frequency.
Figure 12. 12-35 V Input to 5 V Output Application Circuit
Due to the internal design of the TPS5430, there are both upper and lower output voltage limits for any given
input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87%
and is given by:
Where
V
INMIN
= minimum input voltage
I
OMAX
= maximum load current
V
D
= catch diode forward voltage.
R
L
= output inductor series resistance.
This equation assumes maximum on resistance for the internal high side FET.
The lower limit is constrained by the minimum controllable on time which may be as high as 200nsec. The
approximate minimum output voltage for a given input voltage and minimum load current is given by:
Where
V
INMAX
= maximum input voltage
I
OMIN
= minimum load current
V
D
= catch diode forward voltage.
R
L
= output inductor series resistance.
15
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