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TPS3808G33DBVTG4

Part # TPS3808G33DBVTG4
Description SUPERVISORY CIRCUIT - Tape and Reel
Category IC
Availability In Stock
Qty 71
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Texas Instruments
Date Code: 0814
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

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FEATURES
DESCRIPTION
APPLICATIONS
Typical Application Circuit
1.2V 3.3V
TPS3808G12 TPS3808G33 DSP
SENSE V
DD
V
DD
SENSE
V
I/O
V
CORE
GPIO
GNDGNDGND
RESET MR
C
T
C
T
RESET
DBV PACKAGE
SOT23
(TOP VIEW)
V
DD
SENSE
C
T
RESET
GND
MR
1
2
3
6
5
4
RESET
GND
MR
6
5
4
V
DD
SENSE
C
T
1
2
3
DRV PACKAGE
2mm x 2mm QFN
(TOP VIEW)
Power
PAD
TPS3808
SBVS050E MAY 2004 REVISED OCTOBER 2005
Low Quiescent Current, Programmable-Delay
Supervisory Circuit
Power-On Reset Generator with Adjustable
Delay Time: 1.25ms to 10s
The TPS3808xxx family of microprocessor
supervisory circuits monitor system voltages from
Very Low Quiescent Current: 2.4 µ A typ
0.4V to 5.0V, asserting an open drain RESET signal
High Threshold Accuracy: 0.5% typ
when the SENSE voltage drops below a preset
Fixed Threshold Voltages for Standard
threshold or when the manual reset ( MR) pin drops to
Voltage Rails from 0.9V to 5V and Adjustable
a logic low. The RESET output remains low for the
Voltage Down to 0.4V Are Available
user adjustable delay time after the SENSE voltage
and manual reset ( MR) return above their thresholds.
Manual Reset ( MR) Input
Open-Drain RESET Output
The TPS3808 uses a precision reference to achieve
0.5% threshold accuracy for V
IT
3.3V. The reset
Temperature Range: –40 ° C to +125 ° C
delay time can be set to 20ms by disconnecting the
Small SOT23 and 2mm × 2mm QFN Packages
C
T
pin, 300ms by connecting the C
T
pin to V
DD
using
a resistor, or can be user-adjusted between 1.25ms
and 10s by connecting the C
T
pin to an external
DSP or Microcontroller Applications
capacitor. The TPS3808 has a very low typical
quiescent current of 2.4 µ A so it is well-suited to
Notebook/Desktop Computers
battery-powered applications. It is available in a small
PDAs/Hand-Held Products
SOT23 and an ultra-small 2mm × 2mm QFN
Portable/Battery-Powered Products
PowerPAD™ package and is fully specified over a
FPGA/ASIC Applications
temperature range of –40 ° C to +125 ° C (T
J
).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
TPS3808
SBVS050E MAY 2004 REVISED OCTOBER 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
PRODUCT NOMINAL SUPPLY VOLTAGE
(2)
THRESHOLD VOLTAGE (V
IT
)
TPS3808G01 Adjustable 0.405V
TPS3808G09 0.9V 0.84V
TPS3808G12 1.2V 1.12V
TPS3808G15 1.5V 1.40V
TPS3808G18 1.8V 1.67V
TPS3808G25 2.5V 2.33V
TPS3808G30 3.0V 2.79V
TPS3808G33 3.3V 3.07V
TPS3808G50 5.0V 4.65V
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com .
(2) Custom threshold voltages from 0.82V to 3.3V, 4.4V to 5.0V are available through the use of factory EEPROM programming. Minimum
order quantities apply. Contact factory for details and availability.
over operating junction temperature range (unless otherwise noted)
(1)
TPS3808 UNIT
Input voltage range, V
DD
–0.3 to 7.0 V
C
T
voltage range, V
CT
–0.3 to V
DD
+ 0.3 V
Other voltage ranges: V
RESET
, V
MR
, V
SENSE
–0.3 to 7 V
RESET pin current 5 mA
Operating junction temperature range, T
J
(2)
–40 to +150 ° C
Storage temperature range, T
STG
–65 to +150 ° C
ESD rating, HBM 2 kV
ESD rating, CDM 500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) Due to the low dissipated power in this device, it is assumed that T
J
= T
A
.
2
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ELECTRICAL CHARACTERISTICS
TPS3808
SBVS050E MAY 2004 REVISED OCTOBER 2005
1.8V V
DD
6.5V, R
LRESET
= 100k , C
LRESET
= 50pF, over operating temperature range (T
J
= –40 ° C to +125 ° C), unless
otherwise noted. Typical values are at T
J
= +25 ° C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
DD
Input supply range 1.8 6.5 V
V
DD
= 3.3V, RESET not asserted
2.4 5.0 µA
MR, RESET, C
T
open
I
DD
Supply current (current into V
DD
pin)
V
DD
= 6.5V, RESET not asserted
2.7 6.0 µ A
MR, RESET, C
T
open
1.3V V
DD
< 1.8V, I
OL
= 0.4mA 0.3 V
V
OL
Low-level output voltage
1.8V V
DD
6.5V, I
OL
= 1.0mA 0.4 V
Power-up reset voltage
(1)
V
OL
(max) = 0.2V, I
RESET
= 15 µ A 0.8 V
TPS3808G01 –2.0 ± 1.0 +2.0
V
IT
3.3V –1.5 ± 0.5 +1.5
Negative-going
V
IT
input threshold 3.3V < V
IT
5.0V –2.0 ± 1.0 +2.0 %
accuracy
V
IT
3.3V –40 ° C < T
J
< +85 ° C –1.25 ± 0.5 +1.25
3.3V < V
IT
5.0V –40 ° C < T
J
< +85 ° C –1.5 ± 0.5 +1.5
TPS3808G01 1.5 3.0
V
HYS
Hysteresis on V
IT
pin %V
IT
Fixed versions 1.0 2.5
R
MR
MR Internal pull-up resistance 70 90 k
TPS3808G01 V
SENSE
= V
IT
–25 25 nA
Input current at
I
SENSE
SENSE pin
Fixed versions V
SENSE
= 6.5V 1.7 µ A
I
OH
RESET leakage current V
RESET
= 6.5V, RESET not asserted 300 nA
C
T
pin V
IN
= 0V to V
DD
5
Input capacitance,
C
IN
pF
any pin
Other pins V
IN
= 0V to 6.5V 5
V
IL
MR logic low input 0.3 V
DD
V
V
IH
MR logic high input 0.7 V
DD
SENSE V
IH
= 1.05V
IT
, V
IL
= 0.95V
IT
20
Maximum transient
t
w
µ s
duration
MR V
IH
= 0.7V
DD
, V
IL
= 0.3V
DD
0.001
C
T
= Open 12 20 28 ms
C
T
= V
DD
180 300 420 ms
t
d
RESET delay time See timing diagram
C
T
= 100pF 0.75 1.25 1.75 ms
C
T
= 180nF 0.7 1.2 1.7 s
Propagation delay MR to RESET V
IH
= 0.7V
DD
, V
IL
= 0.3V
DD
150 ns
t
pHL
High to low level
SENSE to RESET V
IH
= 1.05V
IT
, V
IL
= 0.95V
IT
20 µ s
RESET delay
θ
JA
Thermal resistance, junction-to-ambient 290 ° C/W
(1) The lowest supply voltage (V
DD
) at which RESET becomes active. T
rise(VDD)
15 µ s/V.
3
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