Introduction

November 2002 − Revised January 2005SPRS205D

Table 2−3. Signal Descriptions (Continued)

TERMINAL

NAME

RESET

CONDITION

‡

FUNCTIONI/O/Z

†

MULTIPLEXED

SIGNAL NAME

PARALLEL BUS (CONTINUED)

C4 I/O/Z

EMIF chip select for memory space CE0 or general-purpose IO9. This pin

serves in one of two functions: EMIF chip select for memory space CE0

(EMIF.CE0) or general-purpose IO9 (GPIO9). The initial state of this pin

depends on the GPIO0 pin. See Section 3.5.1 for more information.

GPIO0 = 1:

Output,

EMIF.CE0

EMIF.CE0 O/Z

Active-low EMIF chip select for memory space CE0. EMIF.CE0 is selected

when the Parallel Port Mode bit field of the External Bus Selection Register

is set to 00 or 01.

EMIF.CE0

GPIO0 = 0:

Input,

GPIO9 I/O/Z

General-purpose IO9. GPIO9 is selected when the Parallel Port Mode bit

field of the External Bus Selection Register is set to 10 or 11.

Input,

GPIO9

C5 I/O/Z

EMIF chip select for memory space CE1 or general-purpose IO10. This pin

serves in one of two functions: EMIF chip-select for memory space CE1

(EMIF.CE1) or general-purpose IO10 (GPIO10). The initial state of this pin

depends on the GPIO0 pin. See Section 3.5.1 for more information.

GPIO0 = 1:

Output,

EMIF.CE1

EMIF.CE1 O/Z

Active-low EMIF chip select for memory space CE1. EMIF.CE1 is selected

when the Parallel Port Mode bit field of the External Bus Selection Register

is set to 00 or 01.

EMIF.CE1

GPIO0 = 0:

Input,

GPIO10 I/O/Z

General-purpose IO10. GPIO10 is selected when the Parallel Port Mode

bit field of the External Bus Selection Register is set to 10 or 11.

Input,

GPIO10

C6 I/O/Z

EMIF chip select for memory space CE2 or HPI control input 0. This pin

serves in one of two functions: EMIF chip-select for memory space CE2

(EMIF.CE2) or HPI control input 0 (HPI.HCNTL0). The initial state of this

pin depends on the GPIO0 pin. See Section 3.5.1 for more information.

GPIO0 = 1:

Output,

EMIF.CE2 O/Z

Active-low EMIF chip select for memory space CE2. EMIF.CE2 is selected

when the Parallel Port Mode bit field of the External Bus Selection Register

is set to 00 or 01.

Output,

EMIF.CE2

GPIO0 = 0:

HPI.HCNTL0 I

HPI control input 0. This pin, in conjunction with HPI.HCNTL1, selects a

host access to one of the three HPI registers. HPI.HCNTL0 is selected

when the Parallel Port Mode bit field of the External Bus Selection Register

is set to 10 or 11.

GPIO0 = 0:

Input,

HPI.HCNTL0

C7 I/O/Z

EMIF chip select for memory space CE3, general-purpose IO11, or HPI

control input 1. This pin serves in one of three functions: EMIF chip-select

for memory space CE3 (EMIF.CE3), general-purpose IO11 (GPIO11), or

HPI control input 1 (HPI.HCNTL1). The initial state of this pin depends on

the GPIO0 pin. See Section 3.5.1 for more information.

GPIO0 = 1:

Output,

EMIF.CE3 O/Z

Active-low EMIF chip select for memory space CE3. EMIF.CE3 is selected

when the Parallel Port Mode bit field is of the External Bus Selection

Output,

EMIF.CE3

GPIO0 = 0:

GPIO11 I/O/Z

General-purpose IO11. GPIO11 is selected when the Parallel Port Mode

bit field is set to 10.

GPIO0 = 0:

Input,

HPI.HCNTL1

HPI.HCNTL1 I

HPI control input 1. This pin, in conjunction with HPI.HCNTL0, selects a

host access to one of the three HPI registers. The HPI.HCNTL1 mode is

selected when the Parallel Port Mode bit field is set to 11.

HPI.HCNTL1

†

I = Input, O = Output, S = Supply, Hi-Z = High-impedance

‡

BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,

PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer

Introduction

November 2002 − Revised January 2005 SPRS205D

Table 2−3. Signal Descriptions (Continued)

TERMINAL

NAME

RESET

CONDITION

‡

FUNCTIONI/O/Z

†

MULTIPLEXED

SIGNAL NAME

PARALLEL BUS (CONTINUED)

C8 I/O/Z

EMIF byte enable 0 control or HPI byte identification. This pin serves in one

of two functions: EMIF byte enable 0 control (EMIF.BE0) or HPI byte

identification (HPI.HBE0). The initial state of this pin depends on the

GPIO0 pin. See Section 3.5.1 for more information.

GPIO0 = 1:

Output,

EMIF.BE0

EMIF.BE0 O/Z

Active-low EMIF byte enable 0 control. EMIF.BE0 is selected when the

Parallel Port Mode bit field of the External Bus Selection Register is set to

00 or 01.

EMIF.BE0

GPIO0 = 0:

Input,

HPI.HBE0 I

HPI byte identification. This pin, in conjunction with HPI.HBE1, identifies

the first or second byte of the transfer. HPI.HBE0 is selected when the

Parallel Port Mode bit field is set to 10 or 11.

Input,

HPI.HBE0

C9 I/O/Z

EMIF byte enable 1 control or HPI byte identification. This pin serves in one

of two functions: EMIF byte enable 1 control (EMIF.BE1) or HPI byte

identification (HPI.HBE1). The initial state of this pin depends on the

GPIO0 pin. See Section 3.5.1 for more information.

GPIO0 = 1:

Output,

EMIF.BE1

EMIF.BE1 O/Z

Active-low EMIF byte enable 1 control. EMIF.BE1 is selected when the

Parallel Port Mode bit field of the External Bus Selection Register is set to

00 or 01.

EMIF.BE1

GPIO0 = 0:

Input,

HPI.HBE1 I

HPI byte identification. This pin, in conjunction with HPI.HBE0, identifies

the first or second byte of the transfer. HPI.HBE1 is selected when the

Parallel Port Mode bit field is set to 10 or 11.

Input,

HPI.HBE1

C10 I/O/Z

EMIF SDRAM row strobe, HPI address strobe, or general-purpose IO12.

This pin serves in one of three functions: EMIF SDRAM row strobe

(EMIF.SDRAS), HPI address strobe (HPI.HAS), or general-purpose IO12

(GPIO12). The initial state of this pin depends on the GPIO0 pin. See

Section 3.5.1 for more information.

GPIO0 = 1:

Output,

EMIF.SDRAS O/Z

Active-low EMIF SDRAM row strobe. EMIF.SDRAS is selected when the

Parallel Port Mode bit field of the External Bus Selection Register is set to

00 or 01.

Output,

EMIF.SDRAS

GPIO0 = 0:

HPI.HAS I

Active-low HPI address strobe. This signal latches the address in the HPIA

Parallel Port Mode bit field is set to 11.

GPIO0 = 0:

Input,

HPI.HAS

GPIO12 I/O/Z

General-purpose IO12. GPIO12 is selected when the Parallel Port Mode

bit field is set to 10.

†

I = Input, O = Output, S = Supply, Hi-Z = High-impedance

‡

BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,

PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer

Introduction

November 2002 − Revised January 2005SPRS205D

Table 2−3. Signal Descriptions (Continued)

TERMINAL

NAME

RESET

CONDITION

‡

FUNCTIONI/O/Z

†

MULTIPLEXED

SIGNAL NAME

PARALLEL BUS (CONTINUED)

C11 I/O/Z

EMIF SDRAM column strobe or HPI chip select input. This pin serves in

one of two functions: EMIF SDRAM column strobe (EMIF.SDCAS) or HPI

chip select input (HPI.HCS). The initial state of this pin depends on the

GPIO0 pin. See Section 3.5.1 for more information.

GPIO0 = 1:

Output,

EMIF.SDCAS

EMIF.SDCAS O/Z

Active-low EMIF SDRAM column strobe. EMIF.SDCAS is selected when

the Parallel Port Mode bit field of the External Bus Selection Register is set

to 00 or 01.

EMIF.SDCAS

GPIO0 = 0:

Input,

HPI.HCS I

HPI Chip Select Input. HPI.HCS is the select input for the HPI and must be

driven low during accesses. HPI.HCS is selected when the Parallel Port

Mode bit field is set to 10 or 11.

Input,

HPI.HCS

C12 I/O/Z

EMIF SDRAM write enable or HPI Data Strobe 1 input. This pin serves in

one of two functions: EMIF SDRAM write enable (EMIF.SDWE) or HPI

data strobe 1 (HPI.HDS1). The initial state of this pin depends on the

GPIO0 pin. See Section 3.5.1 for more information.

GPIO0 = 1:

Output,

EMIF.SDWE

EMIF.SDWE O/Z

EMIF SDRAM write enable. EMIF. SDWE is selected when the Parallel

Port Mode bit field of the External Bus Selection Register is set to 00 or 01.

EMIF.SDWE

GPIO0 = 0:

HPI.HDS1 I

HPI Data Strobe 1 Input. HPI.HDS1 is driven by the host read or write

strobes to control the transfer. HPI.HDS1 is selected when the Parallel

Port Mode bit field is set to 10 or 11.

GPIO0 = 0:

Input,

HPI.HDS1

C13 I/O/Z

SDRAM A10 address line or general-purpose IO13. This pin serves in one

of two functions: SDRAM A10 address line (EMIF.SDA10) or

general-purpose IO13 (GPIO13). The initial state of this pin depends on

the GPIO0 pin. See Section 3.5.1 for more information.

GPIO0 = 1:

Output,

EMIF.SDA10 O/Z

SDRAM A10 address line. Address line/autoprecharge disable for

SDRAM memory. Serves as a row address bit (logically equivalent to A12)

during ACTV commands and also disables the autoprecharging function

of SDRAM during read or write operations. EMIF.SDA10 is selected when

the Parallel Port Mode bit field of the External Bus Selection Register is set

to 00 or 01.

Output,

EMIF.SDA10

GPIO0 = 0:

Input,

GPIO13

GPIO13 I/O/Z

General-purpose IO13. GPIO13 is selected when the Parallel Port Mode

bit field is set to 10 or 11.

C14 I/O/Z

Memory interface clock for SDRAM, HPI Data Strobe 2 input, or

general-purpose IO14. This pin serves in one of two functions: memory

interface clock for SDRAM (EMIF.CLKMEM) or HPI data strobe 2

(HPI.HDS2). The initial state of this pin depends on the GPIO0 pin. See

Section 3.5.1 for more information.

GPIO0 = 1:

Output,

EMIF.CLKMEM

EMIF.CLKMEM O/Z

Memory interface clock for SDRAM. EMIF.CLKMEM is selected when the

Parallel Port Mode bit field of the External Bus Selection Register is set to

00 or 01.

EMIF.CLKMEM

GPIO0 = 0:

Input,

HPI.HDS2 I

HPI Data Strobe 2 Input. HPI.HDS2 is driven by the host read or write

strobes to control the transfer. HPI.HDS2 is selected when the Parallel

Port Mode bit field is set to 10 or 11.

Input,

HPI.HDS2

†

I = Input, O = Output, S = Supply, Hi-Z = High-impedance

‡

BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,

PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer

Part #	TMS320VC5509APGE
Description	FIXED POINT DIGITAL SIGNAL PROCESSOR -DSP, 32 BIT, 200MHZ
Category	IC
Availability	Out of Stock
Qty	0

TMS320VC5509APGE

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