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TMS320VC5509APGE

Part # TMS320VC5509APGE
Description FIXED POINT DIGITAL SIGNAL PROCESSOR -DSP, 32 BIT, 200MHZ
Category IC
Availability Out of Stock
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Electrical Specifications
136
November 2002 − Revised January 2005SPRS205D
5.19 Universal Serial Bus (USB) Timings
Table 5−45 assumes testing over recommended operating conditions (see Figure 5−41 and Figure 5−42).
Table 5−45. Universal Serial Bus (USB) Characteristics
CV
DD
= 1.2 V
CV
DD
= 1.35 V
CV
DD
= 1.6 V
NO. PARAMETER
FULL SPEED
12Mbps
FULL SPEED
12Mbps
UNIT
MIN TYP MAX MIN TYP MAX
U1 t
r
Rise time of DP and DN signals
4 20 4 20 ns
U2 t
f
Fall time of DP and DN signals
4 20 4 20 ns
t
RFM
Rise/Fall time matching
90 111.11 90 111.11 %
V
CRS
Output signal cross-over voltage
1.3 2.0 1.3 2.0 V
t
jr
Differential propagation jitter
§¶
−2 2 −2 2 ns
f
op
Operating frequency (Full speed mode) 12 12 Mb/s
U3 R
s(DP)
Series resistor 24 24
U4 R
s(DN)
Series resistor 24 24
U5 C
edge(DP)
Edge rate control capacitor 22 22 pF
U6 C
edge(DN)
Edge rate control capacitor 22 22 pF
C
L
= 50 pF
(t
r
/t
f
) x 100
§
t
px(1)
− t
px(0)
USB PLL is susceptible to power supply ripple, refer to recommend operating conditions for allowable supply ripple to meet the USB peak-to-peak
jitter specification.
V
OL
U1
U2
V
CRS
V
OH
t
period
+ Jitter
90%
10%
D−
D+
Figure 5−41. USB Timings
Electrical Specifications
137
November 2002 − Revised January 2005 SPRS205D
DP
DN
5509A
PU
USBV
DD
C
L
C
L
D+
D−
U4
U3
R(PU)
1.5 kW
U5
U6
NOTES: A. A full-speed buffer is measured with the load shown.
B. C
L
= 50 pF
Figure 5−42. Full-Speed Loads
Electrical Specifications
138
November 2002 − Revised January 2005SPRS205D
5.20 ADC Timings
Table 5−46 assumes testing over recommended operating conditions.
Table 5−46. ADC Characteristics
NO.
PARAMETER
CV
DD
= 1.2 V
CV
DD
= 1.35 V
CV
DD
= 1.6 V
UNIT
NO.
PARAMETER
MIN MAX MIN MAX
UNIT
A1 t
c(SCLC)
Cycle time, ADC internal conversion clock 500 500 ns
A2 t
d(AQ)
Delay time, ADC sample and hold acquisition time 40 40 µs
A3 t
d(CONV)
Delay time, ADC conversion time 13 * t
c(SCLC)
13 * t
c(SCLC)
ns
A4
S
DNL
Static differential non-linearity error 2 2 LSB
A4
S
DNL
Static integral non-linearity error 3 3 LSB
A5 Z
set
Zero-scale offset error 9 9 LSB
A6 F
set
Full-scale offset error 9 9 LSB
A7 Analog input impedance 1 1 M
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