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TMS320VC5509APGE

Part # TMS320VC5509APGE
Description FIXED POINT DIGITAL SIGNAL PROCESSOR -DSP, 32 BIT, 200MHZ
Category IC
Availability Out of Stock
Qty 0
Qty Price
1 + $22.73692

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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Electrical Specifications
133
November 2002 − Revised January 2005 SPRS205D
Table 5−40. I
2
C Signals (SDA and SCL) Switching Characteristics
CV
DD
= 1.2 V
CV
DD
= 1.35 V
CV
DD
= 1.6 V
NO. PARAMETER
STANDARD
MODE
FAST
MODE
STANDARD
MODE
FAST
MODE
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
IC16 t
c(SCL)
Cycle time, SCL 10 2.5 10 2.5 µs
IC17 t
d(SCLH-SDAL)
Delay time, SCL high to
SDA low for a repeated
START condition
4.7 0.6 4.7 0.6 µs
IC18 t
d(SDAL-SCLL)
Delay time, SDA low to
SCL low for a START and
a repeated START
condition
4 0.6 4 0.6 µs
IC19 t
w(SCLL)
Pulse duration, SCL low 4.7 1.3 4.7 1.3 µs
IC20 t
w(SCLH)
Pulse duration, SCL high 4 0.6 4 0.6 µs
IC21 t
d(SDA-SCLH)
Delay time, SDA valid to
SCL high
250 100 250 100 ns
IC22 t
v(SCLL-SDAV)
Valid time, SDA valid
after SCL low
0 0 0.9 0 0 0.9 µs
IC23 t
w(SDAH)
Pulse duration, SDA high
between STOP and
START conditions
4.7 1.3 4.7 1.3 µs
IC24 t
r(SDA)
Rise time, SDA 1000 20 + 0.1C
b
†
300 1000 20 + 0.1C
b
†
300 ns
IC25 t
r(SCL)
Rise time, SCL 1000 20 + 0.1C
b
†
300 1000 20 + 0.1C
b
†
300 ns
IC26 t
f(SDA)
Fall time, SDA 300 20 + 0.1C
b
†
300 300 20 + 0.1C
b
†
300 ns
IC27 t
f(SCL)
Fall time, SCL 300 20 + 0.1C
b
†
300 300 20 + 0.1C
b
†
300 ns
IC28 t
d(SCLH-SDAH)
Delay time, SCL high to
SDA high for a STOP
condition
4 0.6 4 0.6 µs
IC29 C
p
Capacitance for each
I
2
C pin
10 10 10 10 pF
†
C
b
= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
IC25
IC23
IC19
IC18
IC22
IC27
IC20
IC21
IC17
IC18
IC28
Stop Start Repeated
Start
Stop
SDA
SCL
IC16
IC26 IC24
Figure 5−38. I
2
C Transmit Timings
Electrical Specifications
134
November 2002 − Revised January 2005SPRS205D
5.17 MultiMedia Card (MMC) Timings
Table 5−41 and Table 5−42 assume testing over recommended operating conditions (see Figure 5−39).
Table 5−41. MultiMedia Card (MMC) Timing Requirements
NO.
CV
DD
= 1.2 V
CV
DD
= 1.35 V
CV
DD
= 1.6 V
UNIT
NO.
MIN MAX MIN MAX
UNIT
MMC7 t
su(DV-CLKH)
Setup time, data valid before clock high 9 6 ns
MMC8 t
h(CLKH-DV)
Hold time, data valid after clock high 0 0 ns
Table 5−42. MultiMedia Card (MMC) Switching Characteristics
NO.
PARAMETER
CV
DD
= 1.2 V
CV
DD
= 1.35 V
CV
DD
= 1.6 V
UNIT
NO.
PARAMETER
MIN MAX MIN MAX
UNIT
MMC1 f
(PP)
Clock frequency data transfer mode (PP) (C
L
= 100 pF) 17.2
†
19.2
†
MHz
MMC2 f(
OD)
Clock frequency identification mode (OD) 400 400 kHz
MMC3 t
w(CLKL)
Clock low time (C
L
= 100 pF) 10 10 ns
MMC4 t
w(CLKH)
Clock high time (C
L
= 100 pF) 10 10 ns
MMC5 t
r(CLK)
Clock rise time (C
L
= 100 pF) 10 10 ns
MMC6 t
f(CLK)
Clock fall time (C
L
= 100 pF) 10 10 ns
MMC9 t
d(CLKL-DV)
Delay time, MMC.CLK low to data valid −1 5 −1 5 ns
†
Maximum clock frequency specified in MMC Specification version 3.2 is 20 MHz. The 5509A can support clock frequency as high as 19.2 MHz.
MMC6
MMC5
MMC1
MMC4
MMC8
MMC7
MMC9
MMC.CLK
MMC.CMD
MMC.DATx
MMC.CMD
MMC.DATx
MMC3
Figure 5−39. MultiMedia Card (MMC) Timings
Electrical Specifications
135
November 2002 − Revised January 2005 SPRS205D
5.18 Secure Digital (SD) Card Timings
Table 5−43 and Table 5−44 assume testing over recommended operating conditions (see Figure 5−40).
Table 5−43. Secure Digital (SD) Card Timing Requirements
NO.
CV
DD
= 1.2 V
CV
DD
= 1.35 V
CV
DD
= 1.6 V
UNIT
NO.
MIN MAX MIN MAX
UNIT
SD7 t
su(DV-CLKH)
Setup time, data valid before clock high 9 6 ns
SD8 t
h(CLKH-DV)
Hold time, data valid after clock high 0 0 ns
Table 5−44. Secure Digital (SD) Card Switching Characteristics
NO.
PARAMETER
CV
DD
= 1.2 V
CV
DD
= 1.35 V
CV
DD
= 1.6 V
UNIT
NO.
PARAMETER
MIN MAX MIN MAX
UNIT
SD1 f
(PP)
Clock frequency data transfer mode (PP) (C
L
= 100 pF) 21
†
25
†
MHz
SD2 f(
OD)
Clock frequency identification mode (OD) 400 400 kHz
SD3 t
w(CLKL)
Clock low time (C
L
= 100 pF) 10 10 ns
SD4 t
w(CLKH)
Clock high time (C
L
= 100 pF) 10 10 ns
SD5 t
r(CLK)
Clock rise time (C
L
= 100 pF) 10 10 ns
SD6 t
f(CLK)
Clock fall time (C
L
= 100 pF) 10 10 ns
SD9 t
d(CLKL-DV)
Delay time, SD.CLK low to data valid −1 5 −1 5 ns
†
Maximum clock frequency specified in the SD Specification is 25 MHz. The 5509A can support clock frequency as high as 21.0 MHz at core
voltage = 1.2 V.
SD6
SD5
SD1
SD4
SD8
SD7
SD9
SD.CLK
SD.CMD
SD.DATx
SD.CMD
SD.DATx
SD3
Figure 5−40. Secure Digital (SD) Timings
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