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TMS320VC5509APGE

Part # TMS320VC5509APGE
Description FIXED POINT DIGITAL SIGNAL PROCESSOR -DSP, 32 BIT, 200MHZ
Category IC
Availability Out of Stock
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1 + $22.73692



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Electrical Specifications
127
November 2002 − Revised January 2005 SPRS205D
HR/W
Read Data
HRDY
HCNTL[1:0]
HAS
HCS
HD[15:0]
(read)
E11
E13
E1
E2
Valid (11)
Write Data
HD[15:0]
(write)
E12
E13
E17 E18
Read Write
HDS
E15 E16 E15
E12
E11
E20
E19
E14
E20
E19
Valid (11)
E10
E6
E14
E8E7 E9
HBE[1:0]
Valid Valid
NOTE: The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur concurrent
with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied permanently active and HCS is used as a strobe, the timing
requirements shown for HDS apply to HCS. HRDY is always driven to the same value as its internal state.
Figure 5−33. EHPI Multiplexed Memory (HPID) Read/Write Timings Without Autoincrement
Electrical Specifications
128
November 2002 − Revised January 2005SPRS205D
HR/W
Read Data
n
HRDY
HDS
HAS
HCS
HD[15:0]
(read)
H
PIA contents
n + 1
n + 2
E11 E12
E15 E16
E20
E13
E1
E2
E19
E14
E6
E8E7
Read Data
E1
E2
E6
E8E7
HCNTL[1:0]
Valid (01) Valid (01)
HBE[1:0]
Valid Valid
NOTES: A. During autoincrement mode, although the EHPI internally increments the memory address, reads of the HPIA register by the hos
t
will always indicate the base address.
B. In autoincrement mode, if HBE[1:0] are used to access the data as 8-bit-wide units, the HPIA increments only following each high
byte (HBE1 low) access.
C. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occu
r
concurrent with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied permanently active and HCS is used as a strobe
,
the timing requirements shown for HDS apply to HCS. HRDY is always driven to the same value as its internal state.
Figure 5−34. EHPI Multiplexed Memory (HPID) Read Timings With Autoincrement
Electrical Specifications
129
November 2002 − Revised January 2005 SPRS205D
HR/W
Write DataWrite Data
n
HRDY
HCNTL[1:0]
HDS
HAS
HCS
HD[15:0]
(write)
H
PIA contents
Valid (01) Valid (01)
n + 1
E11
E12
E15 E16
E20
E13
E17 E18
E9
E10 E10
E19
E14
E9
HBE[1:0]
Valid Valid
NOTES: A. During autoincrement mode, although the EHPI internally increments the memory address, reads of the HPIA register by the hos
t
will always indicate the base address.
B. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occu
r
concurrent with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied permanently active and HCS is used as a strobe
,
the timing requirements shown for HDS apply to HCS. HRDY is always driven to the same value as its internal state.
Figure 5−35. EHPI Multiplexed Memory (HPID) Write Timings With Autoincrement
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