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TMS320VC5509APGE

Part # TMS320VC5509APGE
Description FIXED POINT DIGITAL SIGNAL PROCESSOR -DSP, 32 BIT, 200MHZ
Category IC
Availability Out of Stock
Qty 0
Qty Price
1 + $22.73692

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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Electrical Specifications
100
November 2002 − Revised January 2005SPRS205D
M23
M37
M22
M36
CLKMEM
CEx
†
BEx
‡
EMIF.A[13:0]
D[15:0]
SDA10
SDRAS
SDCAS
SDWE
M34
M35
M32
M33
DCAB
†
The chip enable that becomes active depends on the address being accessed.
‡
All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals remain
active until the next access that is not an SDRAM read occurs.
Figure 5−11. SDRAM DCAB Command
Electrical Specifications
101
November 2002 − Revised January 2005 SPRS205D
M23
M37
M22
M36
CLKMEM
CEx
†
BEx
‡
EMIF.A[13:0]
D[15:0]
SDA10
SDRAS
SDCAS
SDWE
M28
M29
REFR
†
The chip enable that becomes active depends on the address being accessed.
‡
All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals
remain active until the next access that is not an SDRAM read occurs.
Figure 5−12. SDRAM REFR Command
Electrical Specifications
102
November 2002 − Revised January 2005SPRS205D
M23
M37
M22
M36
CLKMEM
CEx
†
BEx
‡
EMIF.A[13:0]
D[15:0]
SDA10
SDRAS
SDCAS
SDWE
M32
M33
MRS
MRS Value 0x30
§
M26
M27
M28
M29
†
The chip enable that becomes active depends on the address being accessed.
‡
All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals remain
active until the next access that is not an SDRAM read occurs.
§
Write burst length = 1
Read latency = 3
Burst type = 0 (serial)
Burst length = 1
Figure 5−13. SDRAM MRS Command
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