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TMS320VC5509APGE

Part # TMS320VC5509APGE
Description FIXED POINT DIGITAL SIGNAL PROCESSOR -DSP, 32 BIT, 200MHZ
Category IC
Availability Out of Stock
Qty 0
Qty Price
1 + $22.73692

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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Electrical Specifications
97
November 2002 − Revised January 2005 SPRS205D
M22
M24
M26
M27
M23
M34
M28
M35
M29
M19
M20
D1 D2 D3
CLKMEM
CEx
†
BEx
‡
EMIF.A[13:0]
D[15:0]
SDA10
SDRAS
SDCAS
SDWE
READ READ READ
CA1 CA2 CA3
M21
†
The chip enable that becomes active depends on the address being accessed.
‡
All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals remain
active until the next access that is not an SDRAM read occurs.
Figure 5−8. Three SDRAM Read Commands
Electrical Specifications
98
November 2002 − Revised January 2005SPRS205D
WRITE WRITE WRITE
M22
M24
M26
M30
M34
M28
M32
M25
M27
M31
M23
M35
M29
M33
BE1 BE2 BE3
CA1 CA2 CA3
D1 D2 D3
CLKMEM
CEx
†
BEx
‡
EMIF.A[13:0]
D[15:0]
SDA10
SDRAS
SDCAS
SDWE
†
The chip enable that becomes active depends on the address being accessed.
‡
All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals remain
active until the next access that is not an SDRAM read occurs.
Figure 5−9. Three SDRAM WRT Commands
Electrical Specifications
99
November 2002 − Revised January 2005 SPRS205D
M23
M37
M22
M26
M34
M36
CLKMEM
CEx
†
BEx
‡
EMIF.A[13:0]
D[15:0]
SDA10
SDRAS
SDCAS
SDWE
ACTV
Bank Activate/Row Address
†
The chip enable that becomes active depends on the address being accessed.
‡
All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals remain
active until the next access that is not an SDRAM read occurs.
Figure 5−10. SDRAM ACTV Command
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