Electrical Specifications

November 2002 − Revised January 2005SPRS205D

5.2.2 Recommended Operating Conditions for CV

= 1.35 V (144 MHz)

MIN NOM MAX UNIT

Core

Device supply voltage 1.28 1.35 1.42 V

Peripherals

RCV

RTC module supply voltage, core 1.28 1.35 1.42 V

RDV

RTC module supply voltage, I/O (RTCINX1 and RTCINX2) 1.28 1.35 1.42 V

USBPLLV

USBPLL supply voltage

†

1.28 1.35 1.42 V

USBV

USB module supply voltage, I/O (DP, DN, and PU) 3 3.3 3.6 V

Device supply voltage, I/O (except DP, DN, PU, SDA, SCL)

‡

2.7 3.3 3.6 V

ADV

A/D module digital supply voltage 2.7 3.3 3.6 V

A/D module analog supply voltage 2.7 3.3 3.6 V

Grounds

Supply voltage, GND, I/O, and core 0 V

ADV

Supply voltage, GND, A/D module, digital 0 V

Supply voltage, GND, A/D module, analog 0 V

USBPLLV

Supply voltage, GND, USBPLL 0 V

DN and DP

2.0

High-level input voltage, I/O

SDA & SCL: V

related input

levels

‡

0.7*DV

(max) +0.5

High-level input voltage, I/O

All other inputs

(including hysteresis inputs)

2.0 DV

+ 0.3

DN and DP

0.8

Low-level input voltage, I/O

SDA &SCL: V

related input

levels

‡

−0.5 0.3 * DV

Low-level input voltage, I/O

All other inputs

(including hysteresis inputs)

−0.3 0.8

hys

Hysteresis level Inputs with hysteresis only 0.1*DV

High-level output current

DN and DP

= 2.45 V) −17.0

High-level output current

All other outputs −4

DN and DP

= 0.36 V) 17.0

Low-level output current

SDA and SCL

‡

Low-level output current

All other outputs 4

Operating case temperature −40 85

†

USB PLL is susceptible to power supply ripple. The maximum allowable supply ripple is 1% for 1 Hz to 5 kHz; 1.5% for 5 kHz to 10 MHz; 3%

for 10 MHz to 100 MHz, and less than 5% for 100 MHz or greater.

‡

The I

C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.

Due to the fact that different voltage devices can be connected to the I

C bus, the level of logic 0 (low) and logic 1 (high) are not fixed and

depends on the associated V

USB I/O pins DP and DN can tolerate a short circuit at D+ and D− to 0 V or 5 V, as long as the recommended series resistors (see Figure 5−42)

are connected between the D+ and DP (package), and the D− and DN (package). Do not apply a short circuit to the USB I/O pins DP and DN

in absence of the series resistors.

Electrical Specifications

November 2002 − Revised January 2005 SPRS205D

5.2.3 Recommended Operating Conditions for CV

= 1.6 V (200 MHz)

MIN NOM MAX UNIT

Core

Device supply voltage 1.55 1.6 1.65 V

Peripherals

RCV

RTC module supply voltage, core 1.55 1.6 1.65 V

RDV

RTC module supply voltage, I/O (RTCINX1 and RTCINX2) 1.55 1.6 1.65 V

USBPLLV

USBPLL supply voltage

†

1.55 1.6 1.65 V

USBV

USB module supply voltage, I/O (DP, DN, and PU) 3 3.3 3.6 V

Device supply voltage, I/O (except DP, DN, PU, SDA, SCL)

‡

2.7 3.3 3.6 V

ADV

A/D module digital supply voltage 2.7 3.3 3.6 V

A/D module analog supply voltage 2.7 3.3 3.6 V

Grounds

Supply voltage, GND, I/O, and core 0 V

ADV

Supply voltage, GND, A/D module, digital 0 V

Supply voltage, GND, A/D module, analog 0 V

USBPLLV

Supply voltage, GND, USBPLL 0 V

DN and DP

2.0

High-level input voltage, I/O

SDA & SCL: V

related input

levels

‡

0.7*DV

(max) +0.5

High-level input voltage, I/O

All other inputs

(including hysteresis inputs)

2.0 DV

+ 0.3

DN and DP

0.8

Low-level input voltage, I/O

SDA & SCL: V

related input

levels

‡

−0.5 0.3 * DV

Low-level input voltage, I/O

All other inputs

(including hysteresis inputs)

−0.3 0.8

hys

Hysteresis level Inputs with hysteresis only 0.1*DV

High-level output current

DN and DP

= 2.45 V) −17.0

High-level output current

All other outputs −4

DN and DP

= 0.36 V) 17.0

Low-level output current

SDA and SCL

‡

Low-level output current

All other outputs 4

Operating case temperature −40 85

†

USB PLL is susceptible to power supply ripple. The maximum allowable supply ripple is 1% for 1 Hz to 5 kHz; 1.5% for 5 kHz to 10 MHz; 3%

for 10 MHz to 100 MHz, and less than 5% for 100 MHz or greater.

‡

The I

C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.

Due to the fact that different voltage devices can be connected to the I

C bus, the level of logic 0 (low) and logic 1 (high) are not fixed and

depends on the associated V

USB I/O pins DP and DN can tolerate a short circuit at D+ and D− to 0 V or 5 V, as long as the recommended series resistors (see Figure 5−42)

are connected between the D+ and DP (package), and the D− and DN (package). Do not apply a short circuit to the USB I/O pins DP and DN

in absence of the series resistors.

Electrical Specifications

November 2002 − Revised January 2005SPRS205D

5.3 Electrical Characteristics

5.3.1 Electrical Characteristics Over Recommended Operating Case Temperature

Range for CV

= 1.2 V (108 MHz) (Unless Otherwise Noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DN and DP

†

USBV

= 3.0 V−3.6 V,

= −300 µA

2.8 USBV

High-level output voltage

USBV

= 3.0 V−3.6 V,

= −300 µA

0.9 * USBV

USBV

All other outputs

= 2.7 V−3.6 V,

= MAX

0.75 * DV

SDA & SCL

‡

At 3 mA sink current 0 0.4

Low-level output voltage

DN and DP

†

= 3.0 mA 0.3

Low-level output voltage

All other outputs I

= MAX 0.4

Input current for outputs in

high-impedance

Output-only or

I/O pins with bus

keepers (enabled)

= MAX,

= V

to DV

−300 300

µA

Input current for outputs in

high-impedance

All other output-only

or I/O pins

= MAX

= V

to DV

−5 5

Input pins with

internal pulldown

(enabled)

= MAX,

= V

to DV

30 300

Input current

Input pins with

internal pullup

(enabled)

= MAX,

= V

to DV

−300 −30

µA

Input current

X2/CLKIN

= MAX,

= V

to DV

−50 50

µA

All other input-only

pins

= MAX,

= V

to DV

−5 5

DDC

Supply current, CPU + internal memory access

= 1.2 V

CPU clock = 108 MHz

= 25_C

0.45

mA/

MHz

DDP

supply current, pins active

= 3.3 V

CPU clock = 108 MHz

= 25_C

5.5 mA

DDC

supply current, standby

Oscillator disabled.

All domains in

low-power state

= 1.2 V

= 25_C

100 µA

DDP

supply current, standby

Oscillator disabled.

All domains in

low-power state.

= 3.3 V

No I/O activity

= 25_C

10 µA

Input capacitance 3 pF

Output capacitance 3 pF

†

USB I/O pins DP and DN can tolerate a short circuit at D+ and D− to 0 V or 5 V, as long as the recommended series resistors (see Figure 5−42)

are connected between the D+ and DP (package), and the D− and DN (package). Do not apply a short circuit to the USB I/O pins DP and

DN in absence of the series resistors.

‡

The I

C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.

CPU executing 75% Dual MAC + 25% ADD with moderate data bus activity (table of sine values). CPU and CLKGEN (DPLL) domain are active.

All other domains are idled. See the TMS320VC5509A Power Consumption Summary Application Report (literature number SPRAA04).

One word of a table of a 16-bit sine value is written to the EMIF every 250 ns (64 Mbps). Each EMIF output pin is connected to a 10-pF load.

In CLKGEN domain idle mode, X2/CLKIN becomes output and is driven low to stop external crystals (if used) from oscillating. Standby current

will be higher if an external clock source tries to drive the X2/CLKIN pin during this time.

Part #	TMS320VC5509APGE
Description	FIXED POINT DIGITAL SIGNAL PROCESSOR -DSP, 32 BIT, 200MHZ
Category	IC
Availability	Out of Stock
Qty	0

TMS320VC5509APGE

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