Functional Overview

November 2002 − Revised January 2005 SPRS205D

3.11 Interrupts

Vector-relative locations and priorities for all internal and external interrupts are shown in Table 3−40.

Table 3−40. Interrupt Table

NAME

SOFTWARE

(TRAP)

EQUIVALENT

RELATIVE

LOCATION

†

(HEX BYTES)

PRIORITY FUNCTION

RESET SINT0 0 0 Reset (hardware and software)

NMI

‡

SINT1 8 1 Nonmaskable interrupt

BERR SINT24 C0 2 Bus Error interrupt

INT0 SINT2 10 3 External interrupt #0

INT1 SINT16 80 4 External interrupt #1

INT2 SINT3 18 5 External interrupt #2

TINT0 SINT4 20 6 Timer #0 interrupt

RINT0 SINT5 28 7 McBSP #0 receive interrupt

XINT0 SINT17 88 8 McBSP #0 transmit interrupt

RINT1 SINT6 30 9 McBSP #1 receive interrupt

XINT1/MMCSD1 SINT7 38 10 McBSP #1 transmit interrupt, MMC/SD #1 interrupt

USB SINT8 40 11 USB interrupt

DMAC0 SINT18 90 12 DMA Channel #0 interrupt

DMAC1 SINT9 48 13 DMA Channel #1 interrupt

DSPINT SINT10 50 14 Interrupt from host

INT3/WDTINT SINT11 58 15 External interrupt #3 or Watchdog timer interrupt

INT4/RTC

SINT19 98 16 External interrupt #4 or RTC interrupt

RINT2 SINT12 60 17 McBSP #2 receive interrupt

XINT2/MMCSD2 SINT13 68 18 McBSP #2 transmit interrupt , MMC/SD #2 interrupt

DMAC2 SINT20 A0 19 DMA Channel #2 interrupt

DMAC3 SINT21 A8 20 DMA Channel #3 interrupt

DMAC4 SINT14 70 21 DMA Channel #4 interrupt

DMAC5 SINT15 78 22 DMA Channel #5 interrupt

TINT1 SINT22 B0 23 Timer #1 interrupt

IIC SINT23 B8 24 I

C interrupt

DLOG SINT25 C8 25 Data Log interrupt

RTOS SINT26 D0 26 Real-time Operating System interrupt

− SINT27 D8 27 Software interrupt #27

− SINT28 E0 28 Software interrupt #28

− SINT29 E8 29 Software interrupt #29

− SINT30 F0 30 Software interrupt #30

− SINT31 F8 31 Software interrupt #31

†

Absolute addresses of the interrupt vector locations are determined by the contents of the IVPD and IVPH registers. Interrupt vectors for

interrupts 0−15 and 24−31 are relative to IVPD. Interrupt vectors for interrupts 16−23 are relative to IVPH.

‡

The NMI pin is internally tied high. However, NMI interrupt vector can be used for SINT1 and Watchdog Timer Interrupt.

It is recommended that either the INT4 or RTC interrupt be used. If both INT4 and RTC interrupts are used, one interrupt event can potentially

hold off the other interrupt. For example, if INT4 is asserted first and held low, the RTC interrupt will not be recognized until the INT4 pin is back

to high-logic state again. The INT4 pin must be pulled high if only the RTC interrupt is used.

Functional Overview

November 2002 − Revised January 2005SPRS205D

3.11.1 IFR and IER Registers

The IFR0 (Interrupt Flag Register 0) and IER0 (Interrupt Enable Register 0) bit layouts are shown in

Figure 3−20.

NOTE: Some of the interrupts are shared between multiple interrupt sources. All sources for

a particular bit are internally combined using a logic OR function so that no additional user

configuration is required to select the interrupt source. In the case of the serial port, the shared

functions are mutually exclusive so that only one of the interrupt sources will be active at a time

in a given system. For example: It is not possible to use McBSP2 and MMC/SD2

simultaneously. However, in the case of INT3/WDTINT it is possible to have active interrupts

simultaneously from both the external INT3 source and the watchdog timer. When an interrupt

is detected in this bit, the watchdog timer status register should be polled to determine if the

watchdog timer is the interrupt source.

15 14 13 12 11 10 9 8

DMAC5 DMAC4

XINT2/

MMCSD2

RINT2

INT3/

WDTINT

DSPINT DMAC1 USB

R/W−0 R/W−0 R/W−0 R/W−0 R/W−0 R/W−0 R/W−0 R/W−0

76543210

XINT1/

MMCSD1

RINT1 RINT0 TINT0 INT2 INT0 Reserved

R/W−0 R/W−0 R/W−0 R/W−0 R/W−0 R/W−0 R/W−00

LEGEND: R = Read, W = Write, n = value after reset

Figure 3−20. IFR0 and IER0 Bit Locations

Table 3−41. IFR0 and IER0 Register Bit Fields

BIT

FUNCTION

NUMBER NAME

FUNCTION

15 DMAC5 DMA channel 5 interrupt flag/mask bit

14 DMAC4 DMA channel 4 interrupt flag/mask bit

13 XINT2/MMCSD2

This bit is used as either the McBSP2 transmit interrupt flag/mask bit, the MMC/SD2 interrupt

flag/mask bit.

12 RINT2 McBSP2 receive interrupt flag/mask bit.

11 INT3/WDTINT

This bit is used as either the external user interrupt 3 flag/mask bit, or the watchdog timer interrupt

flag/mask bit.

10 DSPINT HPI host-to-DSP interrupt flag/mask.

9 DMAC1 DMA channel 1 interrupt flag/mask bit

8 USB USB interrupt flag/mask bit.

7 XINT1/MMCSD1

This bit is used as either the McBSP1 transmit interrupt flag/mask bit, the MMC/SD1 interrupt

flag/mask bit.

6 RINT1 McBSP1 receive interrupt flag/mask bit.

5 RINT0 McBSP0 receive interrupt flag bit

4 TINT0 Timer 0 interrupt flag bit

3 INT2 External interrupt 2 flag bit

2 INT0 External interrupt 0 flag bit

1−0 − Reserved for future expansion. These bits should always be written with 0.

Functional Overview

November 2002 − Revised January 2005 SPRS205D

The IFR1 (Interrupt Flag Register 1) and IER1 (Interrupt Enable Register 1) bit layouts are shown in

Figure 3−21.

NOTE: It is possible to have active interrupts simultaneously from both the external interrupt 4

(INT4) and the real-time clock (RTC). When an interrupt is detected in this bit, the real-time

clock status register should be polled to determine if the real-time clock is the source of the

interrupt.

15 11 10 9 8

Reserved RTOS DLOG BERR

R/W−00000

†

R/W−0 R/W−0 R/W−0

76543210

I2C TINT1 DMAC3 DMAC2 INT4/RTC DMAC0 XINT0 INT1

R/W−0 R/W−0 R/W−0 R/W−0 R/W−0 R/W−0 R/W−0 R/W−0

LEGEND: R = Read, W = Write, n = value after reset

†

Always write zeros.

Figure 3−21. IFR1 and IER1 Bit Locations

Table 3−42. IFR1 and IER1 Register Bit Fields

BIT

FUNCTION

NUMBER NAME

FUNCTION

15−11 − Reserved for future expansion. These bits should always be written with 0.

10 RTOS Real-time operating system interrupt flag/mask bit

9 DLOG Data log interrupt flag/mask bit

8 BERR Bus error interrupt flag/mask bit

7 I2C I2C interrupt flag/mask bit

6 TINT1 Timer 1 interrupt flag/mask bit

5 DMAC3 DMA channel 3 interrupt flag/mask bit

4 DMAC2 DMA channel 2 interrupt flag/mask bit

3 INT4/RTC

This bit can be used as either the external user interrupt 4 flag/mask bit, or the real-time clock

interrupt flag/mask bit.

2 DMAC0 DMA channel 0 interrupt flag/mask bit

1 XINT0 McBSP transmit 0 interrupt flag/mask bit

0 INT1 External user interrupt 1 flag/mask bit

Part #	TMS320VC5509APGE
Description	FIXED POINT DIGITAL SIGNAL PROCESSOR -DSP, 32 BIT, 200MHZ
Category	IC
Availability	Out of Stock
Qty	0

TMS320VC5509APGE

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