Functional Overview

November 2002 − Revised January 2005SPRS205D

Table 3−37. USB Module Registers

WORD ADDRESS REGISTER NAME DESCRIPTION

RESET VALUE

†

DMA CONTEXTS

0x5800 Reserved

0x5808 DMAC_O1 Output Endpoint 1 DMA Context Register Undefined

0x5810 DMAC_O2 Output Endpoint 2 DMA Context Register Undefined

0x5818 DMAC_O3 Output Endpoint 3 DMA Context Register Undefined

0x5820 DMAC_O4 Output Endpoint 4 DMA Context Register Undefined

0x5828 DMAC_O5 Output Endpoint 5 DMA Context Register Undefined

0x5830 DMAC_O6 Output Endpoint 6 DMA Context Register Undefined

0x5838 DMAC_O7 Output Endpoint 7 DMA Context Register Undefined

0x5840 Reserved

0x5848 DMAC_I1 Input Endpoint 1 DMA Context Register Undefined

0x5850 DMAC_I2 Input Endpoint 2 DMA Context Register Undefined

0x5858 DMAC_I3 Input Endpoint 3 DMA Context Register Undefined

0x5860 DMAC_I4 Input Endpoint 4 DMA Context Register Undefined

0x5868 DMAC_I5 Input Endpoint 5 DMA Context Register Undefined

0x5870 DMAC_I6 Input Endpoint 6 DMA Context Register Undefined

0x5878 DMAC_I7 Input Endpoint 7 DMA Context Register Undefined

DATA BUFFER

0x5880 Data Buffers Contains X/Y data buffers for endpoints 1 – 7 Undefined

0x6680 OEB_0 Output Endpoint 0 Buffer Undefined

0x66C0 IEB_0 Input Endpoint 0 Buffer Undefined

0x6700 SUP_0 Setup Packet for Endpoint 0 Undefined

ENDPOINT DESCRIPTOR BLOCKS

0x6708 OEDB_1 Output Endpoint 1 Descriptor Register Block Undefined

0x6710 OEDB_2 Output Endpoint 2 Descriptor Register Block Undefined

0x6718 OEDB_3 Output Endpoint 3 Descriptor Register Block Undefined

0x6720 OEDB_4 Output Endpoint 4 Descriptor Register Block Undefined

0x6728 OEDB_5 Output Endpoint 5 Descriptor Register Block Undefined

0x6730 OEDB_6 Output Endpoint 6 Descriptor Register Block Undefined

0x6738 OEDB_7 Output Endpoint 7 Descriptor Register Block Undefined

0x6740 Reserved

0x6748 IEDB_1 Input Endpoint 1 Descriptor Register Block Undefined

0x6750 IEDB_2 Input Endpoint 2 Descriptor Register Block Undefined

0x6758 IEDB_3 Input Endpoint 3 Descriptor Register Block Undefined

0x6760 IEDB_4 Input Endpoint 4 Descriptor Register Block Undefined

0x6768 IEDB_5 Input Endpoint 5 Descriptor Register Block Undefined

0x6770 IEDB_6 Input Endpoint 6 Descriptor Register Block Undefined

0x6778 IEDB_7 Input Endpoint 7 Descriptor Register Block Undefined

†

Hardware reset; x denotes a “don’t care.”

NOTE: The USB module must be brought out of reset by setting bit 2 of the USB Idle Control and Status Register before any USB module register

read or write attempt.

Functional Overview

November 2002 − Revised January 2005 SPRS205D

Table 3−37. USB Module Registers (Continued)

WORD ADDRESS

RESET VALUE

†

DESCRIPTIONREGISTER NAME

CONTROL AND STATUS REGISTERS

0x6780 IEPCNF_0 Input Endpoint 0 Configuration xxxx xxxx 0000 0000

0x6781 IEPBCNT_0 Input Endpoint 0 Byte Count xxxx xxxx 1000 0000

0x6782 OEPCNF_0 Output Endpoint 0 Configuration xxxx xxxx 0000 0000

0x6783 OEPBCNT_0 Output Endpoint 0 Byte Count xxxx xxxx 0000 0000

0x6784 − 0x6790 Reserved

0x6791 GLOBCTL Global Control Register xxxx xxxx 0000 0000

0x6792 VECINT Vector Interrupt Register xxxx xxxx 0000 0000

0x6793 IEPINT Input Endpoint Interrupt Register xxxx xxxx 0000 0000

0x6794 OEPINT Output Endpoint Interrupt Register xxxx xxxx 0000 0000

0x6795 IDMARINT Input DMA Reload Interrupt Register xxxx xxxx 0000 0000

0x6796 ODMARINT Output DMA Reload Interrupt Register xxxx xxxx 0000 0000

0x6797 IDMAGINT Input DMA Go Interrupt Register xxxx xxxx 0000 0000

0x6798 ODMAGINT Output DMA Go Interrupt Register xxxx xxxx 0000 0000

0x6799 IDMAMSK Input DMA Interrupt Mask Register xxxx xxxx 0000 0000

0x679A ODMAMSK Output DMA Interrupt Mask Register xxxx xxxx 0000 0000

0x679B IEDBMSK Input EDB Interrupt Mask Register xxxx xxxx 0000 0000

0x679C OEDBMSK Output EDB Interrupt Mask Register xxxx xxxx 0000 0000

0x67F8 FNUML Frame Number Low Register xxxx xxxx 0000 0000

0x67F9 FNUMH Frame Number High xxxx xxxx xxxx x000

0x67FA PSOFTMR PreSOF Interrupt Timer Register xxxx xxxx 0000 0000

0x67FC USBCTL USB Control Register xxxx xxxx 0101 0000

0x67FD USBMSK USB Interrupt Mask Register xxxx xxxx 0000 0000

0x67FE USBSTA USB Status Register xxxx xxxx 0000 0000

0x67FF FUNADR Function Address Register xxxx xxxx x000 0000

0x7000 USBIDLECTL USB Idle Control and Status Register xxxx xxxx xxxx x000

†

Hardware reset; x denotes a “don’t care.”

NOTE: The USB module must be brought out of reset by setting bit 2 of the USB Idle Control and Status Register before any USB module register

read or write attempt.

Functional Overview

November 2002 − Revised January 2005SPRS205D

Table 3−38. Analog-to-Digital Controller (ADC) Registers

WORD ADDRESS REGISTER NAME DESCRIPTION

RESET VALUE

†

0x6800 ADCCTL[15:11] ADC Control Register 0111 0000 0000 0000

0x6801 ADCDATA[15:0] ADC Data Register 0111 0000 0000 0000

0x6802 ADCCLKDIV[15:0] ADC Function Clock Divider Register 0000 0000 0000 1111

0x6803 ADCCLKCTL[8:0] ADC Clock Control Register 0000 0000 0000 0111

†

Hardware reset; x denotes a “don’t care.”

Table 3−39. External Bus Selection Register

WORD ADDRESS REGISTER NAME DESCRIPTION

RESET VALUE

†

0x6C00 EBSR[15:0] External Bus Selection Register 0000 0000 0000 0011

‡

†

Hardware reset; x denotes a “don’t care.”

‡

The reset value is 0000 0000 0000 0001 if GPIO0 = 1; the value is 0000 0000 0000 0011 if GPIO0 = 0.

Part #	TMS320VC5509APGE
Description	FIXED POINT DIGITAL SIGNAL PROCESSOR -DSP, 32 BIT, 200MHZ
Category	IC
Availability	Out of Stock
Qty	0

TMS320VC5509APGE

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Technical Document