Functional Overview

November 2002 − Revised January 2005 SPRS205D

Table 3−31. GPIO

WORD

ADDRESS

NAME

PIN DESCRIPTION

RESET VALUE

†

0x3400 IODIR[7:0] GPIO[7:0] General-purpose I/O Direction Register 0000 0000 0000 0000

0x3401 IODATA[7:0] GPIO[7:0] General-purpose I/O Data Register 0000 0000 xxxx xxxx

0x4400 AGPIOEN[15:0] A[15:0] Address/GPIO Enable Register 0000 0000 0000 0000

0x4401 AGPIODIR[15:0] A[15:0] Address/GPIO Direction Register 0000 0000 0000 0000

0x4402 AGPIODATA[15:0] A[15:0] Address/GPIO Data Register xxxx xxxx xxxx xxxx

0x4403 EHPIGPIOEN[5:0] GPIO[13:8] EHPI/GPIO Enable Register 0000 0000 0000 0000

0x4404 EHPIGPIODIR[5:0] GPIO[13:8] EHPI/GPIO Direction Register 0000 0000 0000 0000

0x4405 EHPIGPIODATA[5:0] GPIO[13:8] EHPI/GPIO Data Register 0000 0000 00xx xxxx

†

Hardware reset; x denotes a “don’t care.”

Table 3−32. Device Revision ID

WORD ADDRESS REGISTER NAME DESCRIPTION VALUE

‡

0x3803 Rev ID[4:1] Silicon Revision Identification

Rev. 1.0: xxxx xxxx xxx0 000x

Rev. 1.1: xxxx xxxx xxx0 001x

‡

x denotes a “don’t care.”

Table 3−33. I

C Module Registers

WORD ADDRESS REGISTER NAME DESCRIPTION

RESET VALUE

†

0x3C00 I2COAR[9:0]

C Own Address Register 0000 0000 0000 0000

0x3C01 I2CIMR I

C Interrupt Mask Register 0000 0000 0000 0000

0x3C02 I2CSTR I

C Status Register 0000 0001 0000 0000

0x3C03 I2CCLKL[15:0] I

C Clock Divider Low Register 0000 0000 0000 0000

0x3C04 I2CCLKH[15:0] I

C Clock Divider High Register 0000 0000 0000 0000

0x3C05 I2CCNT[15:0] I

C Data Count 0000 0000 0000 0000

0x3C06 I2CDRR[7:0] I

C Data Receive Register 0000 0000 0000 0000

0x3C07 I2CSAR[9:0] I

C Slave Address Register 0000 0011 1111 1111

0x3C08 I2CDXR[7:0] I

C Data Transmit Register 0000 0000 0000 0000

0x3C09 I2CMDR[14:0] I

C Mode Register 0000 0000 0000 0000

0x3C0A I2CIVR I

C Interrupt Vector Register 0000 0000 0000 0000

0x3C0B − Reserved

0x3C0C I2CPSC I

C Prescaler Register 0000 0000 0000 0000

0x3C0D − Reserved

0x3C0E − Reserved

0x3C0F I2CMDR2 I

C Mode Register 2 0000 0000 0000 0000

− I2CRSR I

C Receive Shift Register (not accessible to the CPU)

− I2CXSR I

C Transmit Shift Register (not accessible to the CPU)

†

Hardware reset; x denotes a “don’t care.”

Specifies a unique 5509A I

C address. This register must be set by the programmer. When this device is used in conjunction with another I

master device, the register must be programmed to the I

C slave address (01011xx) allocated by Philips Semiconductor for the 5509A. The

two LSBs are programmable address bits.

NOTE: I

C protocol compatible, no fail-safe buffer.

Functional Overview

November 2002 − Revised January 2005SPRS205D

Table 3−34. Watchdog Timer Registers

WORD ADDRESS REGISTER NAME DESCRIPTION

RESET VALUE

†

0x4000 WDTIM[15:0] WD Timer Counter Register 1111 1111 1111 1111

0x4001 WDPRD[15:0] WD Timer Period Register 1111 1111 1111 1111

0x4002 WDTCR[13:0] WD Timer Control Register 0000 0011 1100 1111

0x4003 WDTCR2[15:0] WD Timer Control Register 2 0001 0000 0000 0000

†

Hardware reset; x denotes a “don’t care.”

Table 3−35. MMC/SD1 Module Registers

WORD ADDRESS REGISTER NAME DESCRIPTION

RESET VALUE

†

0x4800 MMCFCLK[8:0] MMC Function Clock Control Register 0000 0000 0000 0111

0x4801 MMCCTL[10:0] MMC Control Register 0000 0000 0000 0000

0x4802 MMCCLK[8:0] MMC Clock Control Register 0000 0000 0000 1111

0x4803 MMCST0[12:0] MMC Status Register 0 0000 0001 0000 0000

0x4804 MMCST1[5:0] MMC Status Register 1 0000 0000 0000 0000

0x4805 MMCIE[12:0] MMC Interrupt Enable Register 0000 0000 0000 0000

0x4806 MMCTOR[7:0] MMC Response Time-Out Register 0000 0000 0000 0000

0x4807 MMCTOD[15:0] MMC Data Read Time-Out Register 0000 0000 0000 0000

0x4808 MMCBLEN[11:0] MMC Block Length Register 0000 0010 0000 0000

0x4809 MMCNBLK[15:0] MMC Number of Blocks Register 0000 0000 0000 0000

0x480A MMCNBLC[15:0] MMC Number of Blocks Counter Register 0000 0000 0000 0000

0x480B MMCDRR[15:0] MMC Data Receive Register 0000 0000 0000 0000

0x480C MMCDXR[15:0] MMC Data Transmit Register 0000 0000 0000 0000

0x480D MMCCMD[15:0] MMC Command Register 0000 0000 0000 0000

0x480E MMCARGL[15:0] MMC Argument Register − Low 0000 0000 0000 0000

0x480F MMCARGH[15:0] MMC Argument Register − High 0000 0000 0000 0000

0x4810 MMCRSP0[15:0] MMC Response Register 0 0000 0000 0000 0000

0x4811 MMCRSP1[15:0] MMC Response Register 1 0000 0000 0000 0000

0x4812 MMCRSP2[15:0] MMC Response Register 2 0000 0000 0000 0000

0x4813 MMCRSP3[15:0] MMC Response Register 3 0000 0000 0000 0000

0x4814 MMCRSP4[15:0] MMC Response Register 4 0000 0000 0000 0000

0x4815 MMCRSP5[15:0] MMC Response Register 5 0000 0000 0000 0000

0x4816 MMCRSP6[15:0] MMC Response Register 6 0000 0000 0000 0000

0x4817 MMCRSP7[15:0] MMC Response Register 7 0000 0000 0000 0000

0x4818 MMCDRSP[7:0] MMC Data Response Register 0000 0000 0000 0000

0x4819 Reserved

0x481A MMCCIDX[7:0] MMC Command Index Register 0000 0000 0000 0000

†

Hardware reset; x denotes a “don’t care.”

NOTE: The MMC/SD module must be selected in the External Bus Selection Register before any MMC/SD module register read or write attempt.

Functional Overview

November 2002 − Revised January 2005 SPRS205D

Table 3−36. MMC/SD2 Module Registers

WORD ADDRESS REGISTER NAME DESCRIPTION

RESET VALUE

†

0x4C00 MMCFCLK[8:0] MMC Function Clock Control Register 0000 0000 0000 0111

0x4C01 MMCCTL[10:0] MMC Control Register 0000 0000 0000 0000

0x4C02 MMCCLK[8:0] MMC Clock Control Register 0000 0000 0000 1111

0x4C03 MMCST0[12:0] MMC Status Register 0 0000 0001 0000 0000

0x4C04 MMCST1[5:0] MMC Status Register 1 0000 0000 0000 0000

0x4C05 MMCIE[12:0] MMC Interrupt Enable Register 0000 0000 0000 0000

0x4C06 MMCTOR[7:0] MMC Response Time-Out Register 0000 0000 0000 0000

0x4C07 MMCTOD[15:0] MMC Data Read Time-Out Register 0000 0000 0000 0000

0x4C08 MMCBLEN[11:0] MMC Block Length Register 0000 0010 0000 0000

0x4C09 MMCNBLK[15:0] MMC Number of Blocks Register 0000 0000 0000 0000

0x4C0A MMCNBLC[15:0] MMC Number of Blocks Counter Register 0000 0000 0000 0000

0x4C0B MMCDRR[15:0] MMC Data Receive Register 0000 0000 0000 0000

0x4C0C MMCDXR[15:0] MMC Data Transmit Register 0000 0000 0000 0000

0x4C0D MMCCMD[15:0] MMC Command Register 0000 0000 0000 0000

0x4C0E MMCARGL[15:0] MMC Argument Register − Low 0000 0000 0000 0000

0x4C0F MMCARGH[15:0] MMC Argument Register − High 0000 0000 0000 0000

0x4C10 MMCRSP0[15:0] MMC Response Register 0 0000 0000 0000 0000

0x4C11 MMCRSP1[15:0] MMC Response Register 1 0000 0000 0000 0000

0x4C12 MMCRSP2[15:0] MMC Response Register 2 0000 0000 0000 0000

0x4C13 MMCRSP3[15:0] MMC Response Register 3 0000 0000 0000 0000

0x4C14 MMCRSP4[15:0] MMC Response Register 4 0000 0000 0000 0000

0x4C15 MMCRSP5[15:0] MMC Response Register 5 0000 0000 0000 0000

0x4C16 MMCRSP6[15:0] MMC Response Register 6 0000 0000 0000 0000

0x4C17 MMCRSP7[15:0] MMC Response Register 7 0000 0000 0000 0000

0x4C18 MMCDRSP[7:0] MMC Data Response Register 0000 0000 0000 0000

0x4C19 Reserved

0x4C1A MMCCIDX[7:0] MMC Command Index Register 0000 0000 0000 0000

†

Hardware reset; x denotes a “don’t care.”

NOTE: The MMC/SD module must be selected in the External Bus Selection Register before any MMC/SD module register read or write attempt.

Part #	TMS320VC5509APGE
Description	FIXED POINT DIGITAL SIGNAL PROCESSOR -DSP, 32 BIT, 200MHZ
Category	IC
Availability	Out of Stock
Qty	0

TMS320VC5509APGE

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Technical Document