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TMS320VC5509APGE

Part # TMS320VC5509APGE
Description FIXED POINT DIGITAL SIGNAL PROCESSOR -DSP, 32 BIT, 200MHZ
Category IC
Availability Out of Stock
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Functional Overview
64
November 2002 − Revised January 2005SPRS205D
Table 3−28. Multichannel Serial Port #0
PORT ADDRESS
(WORD)
REGISTER NAME DESCRIPTION RESET VALUE
0x2800 DRR2_0[15:0] Data Receive Register 2, McBSP #0 0000 0000 0000 0000
0x2801 DRR1_0[15:0] Data Receive Register 1, McBSP #0 0000 0000 0000 0000
0x2802 DXR2_0[15:0] Data Transmit Register 2, McBSP #0 0000 0000 0000 0000
0x2803 DXR1_0[15:0] Data Transmit Register 1, McBSP #0 0000 0000 0000 0000
0x2804 SPCR2_0[15:0] Serial Port Control Register 2, McBSP #0 0000 0000 0000 0000
0x2805 SPCR1_0[15:0] Serial Port Control Register 1, McBSP #0 0000 0000 0000 0000
0x2806 RCR2_0[15:0] Receive Control Register 2, McBSP #0 0000 0000 0000 0000
0x2807 RCR1_0[15:0] Receive Control Register 1, McBSP #0 0000 0000 0000 0000
0x2808 XCR2_0[15:0] Transmit Control Register 2, McBSP #0 0000 0000 0000 0000
0x2809 XCR1_0[15:0] Transmit Control Register 1, McBSP #0 0000 0000 0000 0000
0x280A SRGR2_0[15:0] Sample Rate Generator Register 2, McBSP #0 0020 0000 0000 0000
0x280B SRGR1_0[15:0] Sample Rate Generator Register 1, McBSP #0 0000 0000 0000 0001
0x280C MCR2_0[15:0] Multichannel Control Register 2, McBSP #0 0000 0000 0000 0000
0x280D MCR1_0[15:0] Multichannel Control Register 1, McBSP #0 0000 0000 0000 0000
0x280E RCERA_0[15:0] Receive Channel Enable Register Partition A, McBSP #0 0000 0000 0000 0000
0x280F RCERB_0[15:0] Receive Channel Enable Register Partition B, McBSP #0 0000 0000 0000 0000
0x2810 XCERA_0[15:0] Transmit Channel Enable Register Partition A, McBSP #0 0000 0000 0000 0000
0x2811 XCERB_0[15:0] Transmit Channel Enable Register Partition B, McBSP #0 0000 0000 0000 0000
0x2812 PCR0[15:0] Pin Control Register, McBSP #0 0000 0000 0000 0000
0x2813 RCERC_0[15:0] Receive Channel Enable Register Partition C, McBSP #0 0000 0000 0000 0000
0x2814 RCERD_0[15:0] Receive Channel Enable Register Partition D, McBSP #0 0000 0000 0000 0000
0x2815 XCERC_0[15:0] Transmit Channel Enable Register Partition C, McBSP #0 0000 0000 0000 0000
0x2816 XCERD_0[15:0] Transmit Channel Enable Register Partition D, McBSP #0 0000 0000 0000 0000
0x2817 RCERE_0[15:0] Receive Channel Enable Register Partition E, McBSP #0 0000 0000 0000 0000
0x2818 RCERF_0[15:0] Receive Channel Enable Register Partition F, McBSP #0 0000 0000 0000 0000
0x2819 XCERE_0[15:0] Transmit Channel Enable Register Partition E, McBSP #0 0000 0000 0000 0000
0x281A XCERF_0[15:0] Transmit Channel Enable Register Partition F, McBSP #0 0000 0000 0000 0000
0x281B RCERG_0[15:0] Receive Channel Enable Register Partition G, McBSP #0 0000 0000 0000 0000
0x281C RCERH_0[15:0] Receive Channel Enable Register Partition H, McBSP #0 0000 0000 0000 0000
0x281D XCERG_0[15:0] Transmit Channel Enable Register Partition G, McBSP #0 0000 0000 0000 0000
0x281E XCERH_0[15:0] Transmit Channel Enable Register Partition H, McBSP #0 0000 0000 0000 0000
Hardware reset; x denotes a “don’t care.”
Functional Overview
65
November 2002 − Revised January 2005 SPRS205D
Table 3−29. Multichannel Serial Port #1
PORT ADDRESS
(WORD)
REGISTER NAME DESCRIPTION
RESET VALUE
0x2C00 DRR2_1[15:0] Data Receive Register 2, McBSP #1 0000 0000 0000 0000
0x2C01 DRR1_1[15:0] Data Receive Register 1, McBSP #1 0000 0000 0000 0000
0x2C02 DXR2_1[15:0] Data Transmit Register 2, McBSP #1 0000 0000 0000 0000
0x2C03 DXR1_1[15:0] Data Transmit Register 1, McBSP #1 0000 0000 0000 0000
0x2C04 SPCR2_1[15:0] Serial Port Control Register 2, McBSP #1 0000 0000 0000 0000
0x2C05 SPCR1_1[15:0] Serial Port Control Register 1, McBSP #1 0000 0000 0000 0000
0x2C06 RCR2_1[15:0] Receive Control Register 2, McBSP #1 0000 0000 0000 0000
0x2C07 RCR1_1[15:0] Receive Control Register 1, McBSP #1 0000 0000 0000 0000
0x2C08 XCR2_1[15:0] Transmit Control Register 2, McBSP #1 0000 0000 0000 0000
0x2C09 XCR1_1[15:0] Transmit Control Register 1, McBSP #1 0000 0000 0000 0000
0x2C0A SRGR2_1[15:0] Sample Rate Generator Register 2, McBSP #1 0020 0000 0000 0000
0x2C0B SRGR1_1[15:0] Sample Rate Generator Register 1, McBSP #1 0000 0000 0000 0001
0x2C0C MCR2_1[15:0] Multichannel Control Register 2, McBSP #1 0000 0000 0000 0000
0x2C0D MCR1_1[15:0] Multichannel Control Register 1, McBSP #1 0000 0000 0000 0000
0x2C0E RCERA_1[15:0] Receive Channel Enable Register Partition A, McBSP #1 0000 0000 0000 0000
0x2C0F RCERB_1[15:0] Receive Channel Enable Register Partition B, McBSP #1 0000 0000 0000 0000
0x2C10 XCERA_1[15:0] Transmit Channel Enable Register Partition A, McBSP #1 0000 0000 0000 0000
0x2C11 XCERB_1[15:0] Transmit Channel Enable Register Partition B, McBSP #1 0000 0000 0000 0000
0x2C12 PCR1[15:0] Pin Control Register, McBSP #1 0000 0000 0000 0000
0x2C13 RCERC_1[15:0] Receive Channel Enable Register Partition C, McBSP #1 0000 0000 0000 0000
0x2C14 RCERD_1[15:0] Receive Channel Enable Register Partition D, McBSP #1 0000 0000 0000 0000
0x2C15 XCERC_1[15:0] Transmit Channel Enable Register Partition C, McBSP #1 0000 0000 0000 0000
0x2C16 XCERD_1[15:0] Transmit Channel Enable Register Partition D, McBSP #1 0000 0000 0000 0000
0x2C17 RCERE_1[15:0] Receive Channel Enable Register Partition E, McBSP #1 0000 0000 0000 0000
0x2C18 RCERF_1[15:0] Receive Channel Enable Register Partition F, McBSP #1 0000 0000 0000 0000
0x2C19 XCERE_1[15:0] Transmit Channel Enable Register Partition E, McBSP #1 0000 0000 0000 0000
0x2C1A XCERF_1[15:0] Transmit Channel Enable Register Partition F, McBSP #1 0000 0000 0000 0000
0x2C1B RCERG_1[15:0] Receive Channel Enable Register Partition G, McBSP #1 0000 0000 0000 0000
0x2C1C RCERH_1[15:0] Receive Channel Enable Register Partition H, McBSP #1 0000 0000 0000 0000
0x2C1D XCERG_1[15:0] Transmit Channel Enable Register Partition G, McBSP #1 0000 0000 0000 0000
0x2C1E XCERH_1[15:0] Transmit Channel Enable Register Partition H, McBSP #1 0000 0000 0000 0000
Hardware reset; x denotes a “don’t care.”
Functional Overview
66
November 2002 − Revised January 2005SPRS205D
Table 3−30. Multichannel Serial Port #2
PORT ADDRESS
(WORD)
REGISTER NAME DESCRIPTION
RESET VALUE
0x3000 DRR2_2[15:0] Data Receive Register 2, McBSP #2 0000 0000 0000 0000
0x3001 DRR1_2[15:0] Data Receive Register 1, McBSP #2 0000 0000 0000 0000
0x3002 DXR2_2[15:0] Data Transmit Register 2, McBSP #2 0000 0000 0000 0000
0x3003 DXR1_2[15:0] Data Transmit Register 1, McBSP #2 0000 0000 0000 0000
0x3004 SPCR2_2[15:0] Serial Port Control Register 2, McBSP #2 0000 0000 0000 0000
0x3005 SPCR1_2[15:0] Serial Port Control Register 1, McBSP #2 0000 0000 0000 0000
0x3006 RCR2_2[15:0] Receive Control Register 2, McBSP #2 0000 0000 0000 0000
0x3007 RCR1_2[15:0] Receive Control Register 1, McBSP #2 0000 0000 0000 0000
0x3008 XCR2_2[15:0] Transmit Control Register 2, McBSP #2 0000 0000 0000 0000
0x3009 XCR1_2[15:0] Transmit Control Register 1, McBSP #2 0000 0000 0000 0000
0x300A SRGR2_2[15:0] Sample Rate Generator Register 2, McBSP #2 0020 0000 0000 0000
0x300B SRGR1_2[15:0] Sample Rate Generator Register 1, McBSP #2 0000 0000 0000 0001
0x300C MCR2_2[15:0] Multichannel Control Register 2, McBSP #2 0000 0000 0000 0000
0x300D MCR1_2[15:0] Multichannel Control Register 1, McBSP #2 0000 0000 0000 0000
0x300E RCERA_2[15:0] Receive Channel Enable Register Partition A, McBSP #2 0000 0000 0000 0000
0x300F RCERB_2[15:0] Receive Channel Enable Register Partition B, McBSP #2 0000 0000 0000 0000
0x3010 XCERA_2[15:0] Transmit Channel Enable Register Partition A, McBSP #2 0000 0000 0000 0000
0x3011 XCERB_2[15:0] Transmit Channel Enable Register Partition B, McBSP #2 0000 0000 0000 0000
0x3012 PCR2[15:0] Pin Control Register, McBSP #2 0000 0000 0000 0000
0x3013 RCERC_2[15:0] Receive Channel Enable Register Partition C, McBSP #2 0000 0000 0000 0000
0x3014 RCERD_2[15:0] Receive Channel Enable Register Partition D, McBSP #2 0000 0000 0000 0000
0x3015 XCERC_2[15:0] Transmit Channel Enable Register Partition C, McBSP #2 0000 0000 0000 0000
0x3016 XCERD_2[15:0] Transmit Channel Enable Register Partition D, McBSP #2 0000 0000 0000 0000
0x3017 RCERE_2[15:0] Receive Channel Enable Register Partition E, McBSP #2 0000 0000 0000 0000
0x3018 RCERF_2[15:0] Receive Channel Enable Register Partition F, McBSP #2 0000 0000 0000 0000
0x3019 XCERE_2[15:0] Transmit Channel Enable Register Partition E, McBSP #2 0000 0000 0000 0000
0x301A XCERF_2[15:0] Transmit Channel Enable Register Partition F, McBSP #2 0000 0000 0000 0000
0x301B RCERG_2[15:0] Receive Channel Enable Register Partition G, McBSP #2 0000 0000 0000 0000
0x301C RCERH_2[15:0] Receive Channel Enable Register Partition H, McBSP #2 0000 0000 0000 0000
0x301D XCERG_2[15:0] Transmit Channel Enable Register Partition G, McBSP #2 0000 0000 0000 0000
0x301E XCERH_2[15:0] Transmit Channel Enable Register Partition H, McBSP #2 0000 0000 0000 0000
Hardware reset; x denotes a “don’t care.”
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