Functional Overview

November 2002 − Revised January 2005SPRS205D

Table 3−24. DMA Configuration Registers (Continued)

PORT ADDRESS

(WORD)

RESET VALUE

†

DESCRIPTIONREGISTER NAME

CHANNEL #1 REGISTERS

0x0C20 DMA_CSDP1 DMA Channel 1 Source Destination

Parameters Register

0000 0000 0000 0000

0x0C21 DMA_CCR1[15:0] DMA Channel 1 Control Register 0000 0000 0000 0000

0x0C22 DMA_CICR1[5:0] DMA Channel 1 Interrupt Control Register xxxx xxxx xx00 0011

0x0C23 DMA_CSR1[6:0] DMA Channel 1 Status Register xxxx xxxx xx00 0000

0x0C24 DMA_CSSA_L1 DMA Channel 1 Source Start Address Register

(lower bits)

Undefined

0x0C25 DMA_CSSA_U1 DMA Channel 1 Source Start Address Register

(upper bits)

Undefined

0x0C26 DMA_CDSA_L1 DMA Channel 1 Source Destination Address Register

(lower bits)

Undefined

0x0C27 DMA_CDSA_U1 DMA Channel 1 Source Destination Address Register

(upper bits)

Undefined

0x0C28 DMA_CEN1 DMA Channel 1 Element Number Register Undefined

0x0C29 DMA_CFN1 DMA Channel 1 Frame Number Register Undefined

0x0C2A DMA_CFI1/

DMA_CSFI1

‡

DMA Channel 1 Frame Index Register/

DMA Channel 1 Source Frame Index Register

‡

Undefined

0x0C2B DMA_CEI1/

DMA_CSEI1

DMA Channel 1 Element Index Register/

DMA Channel 1 Source Element Index Register

Undefined

0x0C2C DMA_CSAC1 DMA Channel 1 Source Address Counter Undefined

0x0C2D DMA_CDAC1 DMA Channel 1 Destination Address Counter Undefined

0x0C2E DMA_CDEI1 DMA Channel 1 Destination Element Index Register Undefined

0x0C2F DMA_CDFI1 DMA Channel 1 Destination Frame Index Register Undefined

†

Hardware reset: x denotes a “don’t care.”

‡

On the TMS320VC5509, the channel frame index applies to both source and destination and this register behaves as DMA_CFIn. On the

TMS320VC5509A, DMA_CSFIn and DMA_CDFIn provide separate source and destination frame indexing. The 5509A can be programmed

for software compatibility with the 5509 through the Software Compatibility Register (DMA_GSCR).

On the TMS320VC5509, the channel element index applies to both source and destination and this register behaves as DMA_CEIn. On the

TMS320VC5509A, DMA_CSEIn and DMA_CDEIn provide separate source and destination frame indexing. The 5509A can be programmed

for software compatibility with the 5509 through the Software Compatibility Register (DMA_GSCR).

Functional Overview

November 2002 − Revised January 2005 SPRS205D

Table 3−24. DMA Configuration Registers (Continued)

PORT ADDRESS

(WORD)

RESET VALUE

†

DESCRIPTIONREGISTER NAME

CHANNEL #2 REGISTERS

0x0C40 DMA_CSDP2 DMA Channel 2 Source Destination

Parameters Register

0000 0000 0000 0000

0x0C41 DMA_CCR2[15:0] DMA Channel 2 Control Register 0000 0000 0000 0000

0x0C42 DMA_CICR2[5:0] DMA Channel 2 Interrupt Control Register xxxx xxxx xx00 0011

0x0C43 DMA_CSR2[6:0] DMA Channel 2 Status Register xxxx xxxx xx00 0000

0x0C44 DMA_CSSA_L2 DMA Channel 2 Source Start Address Register

(lower bits)

Undefined

0x0C45 DMA_CSSA_U2 DMA Channel 2 Source Start Address Register

(upper bits)

Undefined

0x0C46 DMA_CDSA_L2 DMA Channel 2 Source Destination Address Register

(lower bits)

Undefined

0x0C47 DMA_CDSA_U2 DMA Channel 2 Source Destination Address Register

(upper bits)

Undefined

0x0C48 DMA_CEN2 DMA Channel 2 Element Number Register Undefined

0x0C49 DMA_CFN2 DMA Channel 2 Frame Number Register Undefined

0x0C4A DMA_CFI2/

DMA_CSFI2

‡

DMA Channel 2 Frame Index Register/

DMA Channel 2 Source Frame Index Register

‡

Undefined

0x0C4B DMA_CEI2/

DMA_CSEI2

DMA Channel 2 Element Index Register/

DMA Channel 2 Source Element Index Register

Undefined

0x0C4C DMA_CSAC2 DMA Channel 2 Source Address Counter Undefined

0x0C4D DMA_CDAC2 DMA Channel 2 Destination Address Counter Undefined

0x0C4E DMA_CDEI2 DMA Channel 2 Destination Element Index Register Undefined

0x0C4F DMA_CDFI2 DMA Channel 2 Destination Frame Index Register Undefined

†

Hardware reset: x denotes a “don’t care.”

‡

On the TMS320VC5509, the channel frame index applies to both source and destination and this register behaves as DMA_CFIn. On the

TMS320VC5509A, DMA_CSFIn and DMA_CDFIn provide separate source and destination frame indexing. The 5509A can be programmed

for software compatibility with the 5509 through the Software Compatibility Register (DMA_GSCR).

On the TMS320VC5509, the channel element index applies to both source and destination and this register behaves as DMA_CEIn. On the

TMS320VC5509A, DMA_CSEIn and DMA_CDEIn provide separate source and destination frame indexing. The 5509A can be programmed

for software compatibility with the 5509 through the Software Compatibility Register (DMA_GSCR).

Functional Overview

November 2002 − Revised January 2005SPRS205D

Table 3−24. DMA Configuration Registers (Continued)

PORT ADDRESS

(WORD)

RESET VALUE

†

DESCRIPTIONREGISTER NAME

CHANNEL #3 REGISTERS

0x0C60 DMA_CSDP3 DMA Channel 3 Source Destination

Parameters Register

0000 0000 0000 0000

0x0C61 DMA_CCR3[15:0] DMA Channel 3 Control Register 0000 0000 0000 0000

0x0C62 DMA_CICR3[5:0] DMA Channel 3 Interrupt Control Register xxxx xxxx xx00 0011

0x0C63 DMA_CSR3[6:0] DMA Channel 3 Status Register xxxx xxxx xx00 0000

0x0C64 DMA_CSSA_L3 DMA Channel 3 Source Start Address Register

(lower bits)

Undefined

0x0C65 DMA_CSSA_U3 DMA Channel 3 Source Start Address Register

(upper bits)

Undefined

0x0C66 DMA_CDSA_L3 DMA Channel 3 Source Destination Address Register

(lower bits)

Undefined

0x0C67 DMA_CDSA_U3 DMA Channel 3 Source Destination Address Register

(upper bits)

Undefined

0x0C68 DMA_CEN3 DMA Channel 3 Element Number Register Undefined

0x0C69 DMA_CFN3 DMA Channel 3 Frame Number Register Undefined

0x0C6A DMA_CFI3/

DMA_CSFI3

‡

DMA Channel 3 Frame Index Register/

DMA Channel 3 Source Frame Index Register

‡

Undefined

0x0C6B DMA_CEI3/

DMA_CSEI3

DMA Channel 3 Element Index Register/

DMA Channel 3 Source Element Index Register

Undefined

0x0C6C DMA_CSAC3 DMA Channel 3 Source Address Counter Undefined

0x0C6D DMA_CDAC3 DMA Channel 3 Destination Address Counter Undefined

0x0C6E DMA_CDEI3 DMA Channel 3 Destination Element Index Register Undefined

0x0C6F DMA_CDFI3 DMA Channel 3 Destination Frame Index Register Undefined

†

Hardware reset: x denotes a “don’t care.”

‡

On the TMS320VC5509, the channel frame index applies to both source and destination and this register behaves as DMA_CFIn. On the

TMS320VC5509A, DMA_CSFIn and DMA_CDFIn provide separate source and destination frame indexing. The 5509A can be programmed

for software compatibility with the 5509 through the Software Compatibility Register (DMA_GSCR).

On the TMS320VC5509, the channel element index applies to both source and destination and this register behaves as DMA_CEIn. On the

TMS320VC5509A, DMA_CSEIn and DMA_CDEIn provide separate source and destination frame indexing. The 5509A can be programmed

for software compatibility with the 5509 through the Software Compatibility Register (DMA_GSCR).

Part #	TMS320VC5509APGE
Description	FIXED POINT DIGITAL SIGNAL PROCESSOR -DSP, 32 BIT, 200MHZ
Category	IC
Availability	Out of Stock
Qty	0

TMS320VC5509APGE

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