Functional Overview

November 2002 − Revised January 2005 SPRS205D

Table 3−21. CPU Memory-Mapped Registers (Continued)

C55x

BIT FIELDDESCRIPTION

WORD ADDRESS

(HEX)

C54x

CDP − 27 Coefficient Data Pointer [15−0]

AC3L − 28 Accumulator 3 [15−0]

AC3H − 29 [31−16]

AC3G − 2A [39−32]

DPH − 2B Extended Data Page Pointer [6−0]

MDP05 − 2C Reserved [6−0]

MDP67 − 2D Reserved [6−0]

DP − 2E Memory Data Page Start Address [15−0]

PDP − 2F Peripheral Data Page Start Address [8−0]

BK47 − 30 Circular Buffer Size Register for AR[4−7] [15−0]

BKC − 31 Circular Buffer Size Register for CDP [15−0]

BSA01 − 32 Circular Buffer Start Address Register for AR[0−1] [15−0]

BSA23 − 33 Circular Buffer Start Address Register for AR[2−3] [15−0]

BSA45 − 34 Circular Buffer Start Address Register for AR[4−5] [15−0]

BSA67 − 35 Circular Buffer Start Address Register for AR[6−7] [15−0]

BSAC − 36 Circular Buffer Coefficient Start Address Register [15−0]

BIOS − 37 Data Page Pointer Storage Location for 128-word Data Table [15−0]

TRN1 − 38 Transition Register 1 [15−0]

BRC1 − 39 Block Repeat Counter 1 [15−0]

BRS1 − 3A Block Repeat Save 1 [15−0]

CSR − 3B Computed Single Repeat [15−0]

RSA0H − 3C Repeat Start Address 0 [23−16]

RSA0L − 3D [15−0]

REA0H − 3E Repeat End Address 0 [23−16]

REA0L − 3F [15−0]

RSA1H − 40 Repeat Start Address 1 [23−16]

RSA1L − 41 [15−0]

REA1H − 42 Repeat End Address 1 [23−16]

REA1L − 43 [15−0]

RPTC − 44 Repeat Counter [15−0]

IER1 − 45 Interrupt Enable Register 1 [15−0]

IFR1 − 46 Interrupt Flag Register 1 [15−0]

DBIER0 − 47 Debug IER0 [15−0]

DBIER1 − 48 Debug IER1 [15−0]

IVPD − 49 Interrupt Vector Pointer DSP [15−0]

IVPH − 4A Interrupt Vector Pointer HOST [15−0]

ST2_55 − 4B Status Register 2 for C55x [15−0]

SSP − 4C System Stack Pointer [15−0]

SP − 4D User Stack Pointer [15−0]

SPH − 4E Extended Data Page Pointer for the SP and the SSP [6−0]

CDPH − 4F Main Data Page Pointer for the CDP [6−0]

Functional Overview

November 2002 − Revised January 2005SPRS205D

3.10 Peripheral Register Description

Each 5509A device has a set of memory-mapped registers associated with peripherals as listed in Table 3−22

through Table 3−39. Some registers use less than 16 bits. When reading these registers, unused bits are

always read as 0.

NOTE: The CPU access latency to the peripheral memory-mapped registers is 6 CPU cycles.

Following peripheral register update(s), the CPU must wait at least 6 CPU cycles before

attempting to use that peripheral. When more than one peripheral register is updated in a

sequence, the CPU only needs to wait following the final register write. For example, if the

EMIF is being reconfigured, the CPU must wait until the very last EMIF register update takes

effect before trying to access the external memory. The users should consult the respective

peripheral user’s guide to determine if a peripheral requires additional time to initialize itself

to the new configuration after the register updates take effect.

Before reading or writing to the USB register, the USB module has to be brought out of reset by setting bit 2

of the USB Idle Control and Status Register. Likewise, the MMC/SD must be selected by programming the

External Bus Selection Register before reading or writing the MMC/SD module registers.

Table 3−22. Idle Control, Status, and System Registers

WORD ADDRESS REGISTER NAME DESCRIPTION RESET VALUE

†

0x0001 ICR[7:0] Idle Control Register xxxx xxxx 0000 0000

0x0002 ISTR[7:0] Idle Status Register xxxx xxxx 0000 0000

0x07FD SYSR[15:0] System Register 0000 0000 0000 0000

†

Hardware reset; x denotes a “don’t care.”

Table 3−23. External Memory Interface Registers

WORD ADDRESS REGISTER NAME DESCRIPTION RESET VALUE

†

0x0800 EGCR[15:0] EMIF Global Control Register xxxx xxxx 0010 xx00

0x0801 EMI_RST EMIF Global Reset Register xxxx xxxx xxxx xxxx

0x0802 EMI_BE[13:0] EMIF Bus Error Status Register xx00 0000 0000 0000

0x0803 CE0_1[14:0] EMIF CE0 Space Control Register 1 x010 1111 1111 1111

0x0804 CE0_2[15:0] EMIF CE0 Space Control Register 2 0100 1111 1111 1111

0x0805 CE0_3[7:0] EMIF CE0 Space Control Register 3 xxxx xxxx 0000 0000

0x0806 CE1_1[14:0] EMIF CE1 Space Control Register 1 x010 1111 1111 1111

0x0807 CE1_2[15:0] EMIF CE1 Space Control Register 2 0100 1111 1111 1111

0x0808 CE1_3[7:0] EMIF CE1 Space Control Register 3 xxxx xxxx 0000 0000

0x0809 CE2_1[14:0] EMIF CE2 Space Control Register 1 x010 1111 1111 1111

0x080A CE2_2[15:0] EMIF CE2 Space Control Register 2 0101 1111 1111 1111

0x080B CE2_3[7:0] EMIF CE2 Space Control Register 3 xxxx xxxx 0000 0000

0x080C CE3_1[14:0] EMIF CE3 Space Control Register 1 x010 1111 1111 1111

0x080D CE3_2[15:0] EMIF CE3 Space Control Register 2 0101 1111 1111 1111

0x080E CE3_3[7:0] EMIF CE3 Space Control Register 3 xxxx xxxx 0000 0000

0x080F SDC1[15:0] EMIF SDRAM Control Register 1 1111 1001 0100 1000

0x0810 SDPER[11:0] EMIF SDRAM Period Register xxxx 0000 1000 0000

0x0811 SDCNT[11:0] EMIF SDRAM Counter Register xxxx 0000 1000 0000

0x0812 INIT EMIF SDRAM Init Register xxxx xxxx xxxx xxxx

0x0813 SDC2[9:0] EMIF SDRAM Control Register 2 xxxx xx11 1111 1111

0x0814 SDC3 EMIF SDRAM Control Register 3 0000 0000 0000 0111

†

Hardware reset; x denotes a “don’t care.”

Functional Overview

November 2002 − Revised January 2005 SPRS205D

Table 3−24. DMA Configuration Registers

PORT ADDRESS

(WORD)

†

GLOBAL REGISTER

0x0E00 DMA_GCR[2:0] DMA Global Control Register xxxx xxxx xxxx x000

0x0E02 DMA_GSCR DMA Software Compatibility Register

0x0E03 DMA_GTCR DMA Timeout Control Register

CHANNEL #0 REGISTERS

0x0C00 DMA_CSDP0 DMA Channel 0 Source Destination

Parameters Register

0000 0000 0000 0000

0x0C01 DMA_CCR0[15:0] DMA Channel 0 Control Register 0000 0000 0000 0000

0x0C02 DMA_CICR0[5:0] DMA Channel 0 Interrupt Control Register xxxx xxxx xx00 0011

0x0C03 DMA_CSR0[6:0] DMA Channel 0 Status Register xxxx xxxx xx00 0000

0x0C04 DMA_CSSA_L0 DMA Channel 0 Source Start Address Register

(lower bits)

Undefined

0x0C05 DMA_CSSA_U0 DMA Channel 0 Source Start Address Register

(upper bits)

Undefined

0x0C06 DMA_CDSA_L0 DMA Channel 0 Source Destination Address Register

(lower bits)

Undefined

0x0C07 DMA_CDSA_U0 DMA Channel 0 Source Destination Address Register

(upper bits)

Undefined

0x0C08 DMA_CEN0 DMA Channel 0 Element Number Register Undefined

0x0C09 DMA_CFN0 DMA Channel 0 Frame Number Register Undefined

0x0C0A DMA_CFI0/

DMA_CSFI0

‡

DMA Channel 0 Frame Index Register/

DMA Channel 0 Source Frame Index Register

‡

Undefined

0x0C0B DMA_CEI0/

DMA_CSEI0

DMA Channel 0 Element Index Register/

DMA Channel 0 Source Element Index Register

Undefined

0x0C0C DMA_CSAC0 DMA Channel 0 Source Address Counter Undefined

0x0C0D DMA_CDAC0 DMA Channel 0 Destination Address Counter Undefined

0x0C0E DMA_CDEI0 DMA Channel 0 Destination Element Index Register Undefined

0x0C0F DMA_CDFI0 DMA Channel 0 Destination Frame Index Register Undefined

†

Hardware reset: x denotes a “don’t care.”

‡

On the TMS320VC5509, the channel frame index applies to both source and destination and this register behaves as DMA_CFIn. On the

TMS320VC5509A, DMA_CSFIn and DMA_CDFIn provide separate source and destination frame indexing. The 5509A can be programmed

for software compatibility with the 5509 through the Software Compatibility Register (DMA_GSCR).

On the TMS320VC5509, the channel element index applies to both source and destination and this register behaves as DMA_CEIn. On the

TMS320VC5509A, DMA_CSEIn and DMA_CDEIn provide separate source and destination frame indexing. The 5509A can be programmed

for software compatibility with the 5509 through the Software Compatibility Register (DMA_GSCR).

Part #	TMS320VC5509APGE
Description	FIXED POINT DIGITAL SIGNAL PROCESSOR -DSP, 32 BIT, 200MHZ
Category	IC
Availability	Out of Stock
Qty	0

TMS320VC5509APGE

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