Functional Overview

November 2002 − Revised January 2005SPRS205D

15 3210

Reserved DPLLSTAT APLLSTAT PLLSEL

R, 0000 0000 0000 0 R, 1 R, 0 R/W, 0

LEGEND: R = Read, W = Write, n = value after reset

Figure 3−18. USB PLL Selection and Status Register Bit Layout

Table 3−18. USB PLL Selection and Status Register Bit Functions

BIT

NO.

BIT

NAME

RESET

VALUE

FUNCTION

15−3 Reserved 0 Reserved bits. Always write 0.

2 DPLLSTAT 1

Status bit indicating if the DPLL is the source for the USB module clock.

DPLLSTAT = 0 The DPLL is not the USB module clock source.

DPLLSTAT = 1 The DPLL is the USB module clock source.

1 APLLSTAT 0

Status bit indicating if the APLL is the source for the USB module clock.

APLLSTAT = 0 The APLL is not the USB module clock source.

APLLSTAT = 1 The APLL is the USB module clock source.

0 PLLSEL 0

USB module clock source selection bit.

PLLSEL = 0 DPLL is selected as USB module clock source.

PLLSEL = 1 APLL is selected as USB module clock source.

15 12 11 10 3 2 1 0

MULT DIV COUNT ON MODE STAT

R/W, 0000 R/W, 0 R, 0000 0000 R/W, 0 R/W, 0 R, 0

LEGEND: R = Read, W = Write, n = value after reset

Figure 3−19. USB APLL Clock Mode Register Bit Layout

Table 3−19. USB APLL Clock Mode Register Bit Functions

BIT

NO.

BIT

NAME

RESET

VALUE

FUNCTION

15−12 MULT 0

PLL Multiply Factor K. Multiply Factor K, combined with DIV and MODE, determines the final PLL output

clock frequency.

K = MULT[3:0] + 1

11 DIV 0

PLL Divide Factor (D) selection bit for PLL multiply mode operation. DIV, combined with K and MODE,

determines the final PLL output clock frequency. When the PLL is operating in multiply mode:

DIV = 0 PLL Divide Factor D = 1

DIV = 1 PLL Divide Factor D = 2 if K is odd

PLL Divide Factor D = 4 if K is even

10−3 COUNT 0

8-bit counter for PLL lock timer. When the MODE bit is set to 1, the COUNT field starts decrementing by 1

at the rate of CLKIN/16. When COUNT decrements to 0, the STAT bit is set to 1 and the PLL enabled clock

is sourced to the USB module.

Functional Overview

November 2002 − Revised January 2005 SPRS205D

Table 3−19. USB APLL Clock Mode Register Bit Functions (Continued)

BIT

NO.

FUNCTION

RESET

VALUE

BIT

NAME

2 ON 0

PLL Voltage Controlled Oscillator (VCO) enable bit. This bit works in conjunction with MODE to enable

or disable the VCO.

ON MODE VCO

0 0 OFF

1 X ON

X 1 ON

X = Don’t care

1 MODE 0

PLL mode selection bit

MODE = 0 PLL operating in divide mode (VCO bypassed). When the PLL is operating in DIV mode, the

PLL Divide Factor (D) is determined by the factor K.

D = 2 if K = 1 to 15

D = 4 if K = 16

MODE = 1 PLL operating in multiply mode (VCO on). The PLL multiply and divide factors are

determined by DIV and K.

0 STAT 0

PLL lock status bit

STAT = 0 PLL operating in DIV mode (VCO bypassed)

STAT = 1 PLL operating in multiply mode (VCO on)

DIV, combined with MODE and K, defines the final PLL multiplication ratio M/D as indicated below. The USB

APLL clock frequency can be simply expressed by:

USB APLL CLK

= F

CLKIN

x (M/D)

The multiplication factor M and the dividing factor D are defined in Table 3−20.

Table 3−20. M and D Values Based on MODE, DIV, and K

MODE DIV K M D

0 X 1 to 15 1 2

0 X 16 1 4

1 0 1 to 15 K 1

1 0 16 1 1

1 1 Odd K 2

1 1 Even K − 1 4

The USB clock generation and the PLL switching scheme are discussed in detail in the TMS320VC5507/5509

DSP Universal Serial Bus (USB) Module Reference Guide (literature number SPRU596) and in the Using the

USB APLL on the TMS320VC5507/5509A Application Report (literature number SPRA997).

Functional Overview

November 2002 − Revised January 2005SPRS205D

3.9 Memory-Mapped Registers

The 5509A has 78 memory-mapped CPU registers that are mapped in data memory space address 0h to 4Fh.

Table 3−21 provides a list of the CPU memory-mapped registers (MMRs) available. The corresponding

TMS320C54x (C54x) CPU registers are also indicated where applicable.

Table 3−21. CPU Memory-Mapped Registers

C55x

C54x

WORD ADDRESS

(HEX)

DESCRIPTION BIT FIELD

IER0 IMR 00 Interrupt Enable Register 0 [15−0]

IFR0 IFR 01 Interrupt Flag Register 0 [15−0]

ST0_55 − 02 Status Register 0 for C55x [15−0]

ST1_55 − 03 Status Register 1 for C55x [15−0]

ST3_55 − 04 Status Register 3 for C55x [15−0]

− − 05 Reserved [15−0]

ST0 ST0 06 Status Register ST0 [15−0]

ST1 ST1 07 Status Register ST1 [15−0]

AC0L AL 08 Accumulator 0 [15−0]

AC0H AH 09 [31−16]

AC0G AG 0A [39−32]

AC1L BL OB Accumulator 1 [15−0]

AC1H BH 0C [31−16]

AC1G BG 0D [39−32]

T3 TREG 0E Temporary Register [15−0]

TRN0 TRN 0F Transition Register [15−0]

AR0 AR0 10 Auxiliary Register 0 [15−0]

AR1 AR1 11 Auxiliary Register 1 [15−0]

AR2 AR2 12 Auxiliary Register 2 [15−0]

AR3 AR3 13 Auxiliary Register 3 [15−0]

AR4 AR4 14 Auxiliary Register 4 [15−0]

AR5 AR5 15 Auxiliary Register 5 [15−0]

AR6 AR6 16 Auxiliary Register 6 [15−0]

AR7 AR7 17 Auxiliary Register 7 [15−0]

SP SP 18 Stack Pointer Register [15−0]

BK03 BK 19 Circular Buffer Size Register [15−0]

BRC0 BRC 1A Block Repeat Counter [15−0]

RSA0L RSA 1B Block Repeat Start Address [15−0]

REA0L REA 1C Block Repeat End Address [15−0]

PMST PMST 1D Processor Mode Status Register [15−0]

XPC XPC 1E Program Counter Extension Register [7−0]

− − 1F Reserved [15−0]

T0 − 20 Temporary Data Register 0 [15−0]

T1 − 21 Temporary Data Register 1 [15−0]

T2 − 22 Temporary Data Register 2 [15−0]

T3 − 23 Temporary Data Register 3 [15−0]

AC2L − 24 Accumulator 2 [15−0]

AC2H − 25 [31−16]

AC2G − 26 [39−32]

TMS320C54x and C54x are trademarks of Texas Instruments.

Part #	TMS320VC5509APGE
Description	FIXED POINT DIGITAL SIGNAL PROCESSOR -DSP, 32 BIT, 200MHZ
Category	IC
Availability	Out of Stock
Qty	0

TMS320VC5509APGE

Related Items

Technical Document