Functional Overview

November 2002 − Revised January 2005 SPRS205D

3.2 Peripherals

The 5509A supports the following peripherals:

• A Configurable Parallel External Interface supporting either:

− 16-bit external memory interface (EMIF) for asynchronous memory and/or SDRAM

− 16-bit enhanced host-port interface (HPI)

• A six-channel direct memory access (DMA) controller

• A programmable phase-locked loop clock generator

• Two 20-bit timers

• Watchdog Timer

• Three serial ports supporting a combination of:

− up to three multichannel buffered serial ports (McBSPs)

− up to two MultiMedia/Secure Digital Card Interfaces

• Seven (LQFP) or Eight (BGA) configurable general-purpose I/O pins

• USB full-speed slave interface supporting:

− Bulk

− Interrupt

− Isochronous

• I

C multi-master and slave interface (I

C compatible except, no fail-safe I/O buffers)

• Real-time clock with crystal input, separate clock domain and supply pins

• 4-channel (BGA) or 2-channel (LQFP)10-bit Successive Approximation A/D

For detailed information on the C55x DSP peripherals, see the following documents:

• TMS320C55x DSP Functional Overview (literature number SPRU312)

• TMS320C55x DSP Peripherals Overview Reference Guide (literature number SPRU317)

3.3 Direct Memory Access (DMA) Controller

The 5509A DMA provides the following features:

• Four standard ports, one for each of the following data resources: DARAM, SARAM, Peripherals and

External Memory

• Six channels, which allow the DMA controller to track the context of six independent DMA channels

• Programmable low/high priority for each DMA channel

• One interrupt for each DMA channel

• Event synchronization. DMA transfers in each channel can be dependent on the occurrence of selected

events.

• Programmable address modification for source and destination addresses

• Dedicated Idle Domain allows the DMA controller to be placed in a low-power (idle) state under software

control.

• Dedicated DMA channel used by the HPI to access internal memory (DARAM)

The 5509A DMA controller allows transfers to be synchronized to selected events. The 5509A supports

19 separate sync events and each channel can be tied to separate sync events independent of the other

channels. Sync events are selected by programming the SYNC field in the channel-specific DMA Channel

Control Register (DMA_CCR).

Functional Overview

November 2002 − Revised January 2005SPRS205D

3.3.1 DMA Channel Control Register (DMA_CCR)

The channel control register (DMA_CCR) bit layouts are shown in Figure 3−4.

15 14 13 12 11 10 9 8

DST AMODE SRC AMODE END PROG Reserved REPEAT AUTO INIT

R/W, 00 R/W, 00 R/W, 0 R, 0 R/W, 0 R/W, 0

7654 0

EN PRIO FS SYNC

R/W, 0 R/W, 0 R/W, 0 R/W, 00000

LEGEND: R = Read, W = Write, n = value after reset

Figure 3−4. DMA_CCR Bit Locations

The SYNC[4:0] bits specify the event that can initiate the DMA transfer for the corresponding DMA channel.

The five bits allow several configurations as listed in Table 3−4. The bits are set to zero upon reset. For those

synchronization modes with more than one peripheral listed, the Serial Port Mode bit field of the External Bus

Selection Register dictates which peripheral event is actually connected to the DMA input.

Table 3−4. Synchronization Control Function

SYNC FIELD IN

DMA_CCR

SYNCHRONIZATION MODE

00000b No event synchronized

00001b McBSP 0 Receive Event (REVT0)

00010b McBSP 0 Transmit Event (XEVT0)

00011b Reserved. These bits should always be written with 0.

00100b Reserved. These bits should always be written with 0.

00101b

McBSP1/MMC−SD1 Receive Event

Serial Port 1 Mode:

00 = McBSP1 Receive Event (REVT1)

01 = MMC/SD1 Receive Event (RMMCEVT1)

10 = Reserved

11 = Reserved

00110b

McBSP1/MMC−SD1 Transmit Event

Serial Port 1 Mode:

00 = McBSP1 Transmit Event (XEVT1)

01 = MMC/SD1 Transmit Event (XMMCEVT1)

10 = Reserved

11 = reserved

00111b Reserved. These bits should always be written with 0.

01000b Reserved. These bits should always be written with 0.

01001b

McBSP2/MMC−SD2 Receive Event

Serial Port 2 Mode:

00 = McBSP2 Receive Event (REVT2)

01 = MMC/SD2 Receive Event (RMMCEVT2)

10 = Reserved

11 = Reserved

†

The I

C receive event (REVTI2C) and external interrupt 4 (INT4) share a synchronization input to the DMA. When the SYNC field of the

DMA_CCR is set to 10011b, the logical OR of these two sources is used for DMA synchronization.

Functional Overview

November 2002 − Revised January 2005 SPRS205D

Table 3−4. Synchronization Control Function (Continued)

SYNC FIELD IN

DMA_CCR

SYNCHRONIZATION MODE

01010b

McBSP2/MMC−SD2 Transmit Event

Serial Port 2 Mode:

00 = McBSP2 Transmit Event (XEVT2)

01 = MMC/SD2 Transmit Event (XMMCEVT2)

10 = Reserved

11 = Reserved

01011b Reserved. These bits should always be written with 0.

01100b Reserved. These bits should always be written with 0.

01101b Timer 0 Interrupt Event

01110b Timer 1 Interrupt Event

01111b External Interrupt 0

10000b External Interrupt 1

10001b External Interrupt 2

10010b External Interrupt 3

10011b External Interrupt 4 / I

C Receive Event (REVTI2C)

†

10100b I

C Transmit Event (XEVTI2C)

Other values Reserved (Do not use these values)

†

The I

C receive event (REVTI2C) and external interrupt 4 (INT4) share a synchronization input to the DMA. When the SYNC field of the

DMA_CCR is set to 10011b, the logical OR of these two sources is used for DMA synchronization.

3.4 I

C Interface

The TMS320VC5509A includes an I

C serial port. The I

C port supports:

• Compatible with Philips I

C Specification Revision 2.1 (January 2000)

• Operates at 100 Kbps or 400 Kbps

• 7-bit addressing mode

• Master (transmit/receive) and slave (transmit/receive) modes of operation

• Events: DMA, interrupt, or polling

The I

C module clock must be in the range from 7 MHz to 12 MHz. This is necessary for proper operation of

the I

C module. With the I

C module clock in this range, the noise filters on the SDA and SCL pins suppress

noise that has a duration of 50 ns or shorter. The I

C module clock is derived from the DSP clock divided by

a programmable prescaler.

NOTE: I/O buffers are not fail-safe. The SDA and SCL pins could potentially draw current if the

device is powered down and SDA and SCL are driven by other devices connected to the I

C bus.

3.5 Configurable External Buses

The 5509A offers several combinations of configurations for its external parallel port and two serial ports. This

allows the system designer to choose the appropriate media interface for its application without the need of

a large-pin-count package. The External Bus Selection Register controls the routing of the parallel and serial

port signals.

Part #	TMS320VC5509APGE
Description	FIXED POINT DIGITAL SIGNAL PROCESSOR -DSP, 32 BIT, 200MHZ
Category	IC
Availability	Out of Stock
Qty	0

TMS320VC5509APGE

Related Items

Technical Document