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TMS320VC5509APGE

Part # TMS320VC5509APGE
Description FIXED POINT DIGITAL SIGNAL PROCESSOR -DSP, 32 BIT, 200MHZ
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Functional Overview
34
November 2002 − Revised January 2005SPRS205D
3.1.4.1 PGE Package Memory Map
The PGE package features 14 address bits representing 16K-byte linear address for asynchronous memories
per CE space. Due to address row/column multiplexing, address reach for SDRAM devices is 4M bytes for
each CE space. The largest SDRAM device that can be used with the 5509A in a PGE package is 128M-bit
SDRAM.
000000
DARAM / HPI Access
(32K − 192) Bytes
008000
DARAM
32K Bytes
010000
SARAM
§
192K Bytes
External
− CE0
040000
400000
800000
C00000
FF0000
FF8000
32K Bytes
FFC000
16K Bytes
16K Bytes
F
FFFFF
External
− CE1
External
− CE2
External
− CE3
Block Size
Byte Address
(Hex)
(if MPNMC=0)
ROM
||
(if MPNMC=0)
ROM
||
(if MPNMC=1)
External
− CE3
(if MPNMC=1)
External
− CE3
(if MPNMC=1)
External
− CE3
16K Bytes − Asynchronous
4M Bytes − SDRAM (MPNMC = 1)
4M Bytes − 64K Bytes if internal ROM selected (MPNMC = 0)
16K Bytes − Asynchronous
4M Bytes − SDRAM
16K Bytes − Asynchronous
4M Bytes − SDRAM
16K Bytes − Asynchronous
4M Bytes − 256K Bytes SDRAM
#
Memory Blocks
Address shown represents the first byte address in each block.
Dual-access RAM (DARAM): two accesses per cycle per block, 8 blocks of 8K bytes.
§
Single-access RAM (SARAM): one access per cycle per block, 24 blocks of 8K bytes.
External memory spaces are selected by the chip-enable signal shown (CE[0:3]). Supported memory types include: asynchronous static
RAM (SRAM) and synchronous DRAM (SDRAM).
#
The minus 256K bytes consists of 32K-byte DARAM/HPI access, 32K-byte DARAM, and 192K-byte SARAM.
||
Read-only memory (ROM): one access every two cycles, two blocks of 32K bytes.
0000C0
MMR (Reserved)
Figure 3−2. TMS320VC5509A Memory Map (PGE Package)
Functional Overview
35
November 2002 − Revised January 2005 SPRS205D
3.1.4.2 GHH and ZHH Package Memory Map
The GHH and ZHH packages feature 21 address bits representing 2M-byte linear address for asynchronous
memories per CE space. Due to address row/column multiplexing, address reach for SDRAM devices is
4M bytes for each CE space. The largest SDRAM device that can be used with the 5509A in a GHH or ZHH
package is 128M-bit SDRAM.
000000
DARAM / HPI Access
(32K − 192) Bytes
008000
DARAM
32K Bytes
010000
SARAM
§
192K Bytes
External
− CE0
040000
400000
800000
C00000
FF0000
FF8000
32K Bytes
FFC000
16K Bytes
16K Bytes
F
FFFFF
External
− CE1
External
− CE2
External
− CE3
Block Size
Byte Address
(Hex)
(if MPNMC=0)
ROM
||
(if MPNMC=0)
ROM
||
(if MPNMC=1)
External
− CE3
(if MPNMC=1)
External
− CE3
(if MPNMC=1)
External
− CE3
2M Bytes − Asynchronous
4M Bytes − SDRAM (MPNMC = 1)
4M Bytes − 64K Bytes if internal ROM selected (MPNMC = 0)
2M Bytes − Asynchronous
4M Bytes − SDRAM
2M Bytes − Asynchronous
4M Bytes − SDRAM
2M Bytes − Asynchronous
4M Bytes − 256K Bytes SDRAM
#
Memory Blocks
Address shown represents the first byte address in each block.
Dual-access RAM (DARAM): two accesses per cycle per block, 8 blocks of 8K bytes.
§
Single-access RAM (SARAM): one access per cycle per block, 24 blocks of 8K bytes.
External memory spaces are selected by the chip-enable signal shown (CE[0:3]). Supported memory types include: asynchronous static
RAM (SRAM) and synchronous DRAM (SDRAM).
#
The minus 256K bytes consists of 32K-byte DARAM/HPI access, 32K-byte DARAM, and 192K-byte SARAM.
||
Read-only memory (ROM): one access every two cycles, two blocks of 32K bytes.
0000C0
MMR (Reserved)
Figure 3−3. TMS320VC5509A Memory Map (GHH and ZHH Packages)
Functional Overview
36
November 2002 − Revised January 2005SPRS205D
3.1.5 Boot Configuration
The on-chip bootloader provides a method to transfer application code and tables from an external source to
the on-chip RAM memory at power up. These options include:
Enhanced host-port interface (HPI) in multiplexed or nonmultiplexed mode
External asynchronous memory boot (via the EMIF) from 8-bit-wide or 16-bit-wide memory
Serial port boot (from McBSP0) with 8-bit or 16-bit data length
Serial EPROM boot (from McBSP0) supporting EPROMs with 16-bit or 24-bit address
USB boot
I
2
C EEPROM
Direct execution from external 16-bit-wide asynchronous memory
External pins select the boot configuration. The values of GPIO[3:0] are sampled, following reset, upon
execution of the on-chip bootloader code. It is not possible to disable the bootloader at reset because the
5509A always starts execution from the on-chip ROM following a hardware reset. A summary of boot
configurations is shown in Table 3−3. For more information on using the bootloader, see the Using the
TMS320VC5503/VC5507/VC5509/VC5509A Bootloader Application Report (literature number SPRA375).
Table 3−3. Boot Configuration Summary
GPIO0 GPIO3 GPIO2
GPIO1
BOOT MODE PROCESS
0 0 0 0 Reserved
0 0 0 1 Serial (SPI) EPROM Boot (24-bit address) via McBSP0
0 0 1 0 USB
0 0 1 1 I
2
C EEPROM (7-bit address)
0 1 0 0 Reserved
0 1 0 1 HPI – multiplexed mode
0 1 1 0 HPI – nonmultiplexed mode
0 1 1 1 Reserved
1 0 0 0 Execute from 16-bit-wide asynchronous memory (on CE1 space)
1 0 0 1 Serial (SPI) EPROM Boot (16-bit address) via McBSP0
1 0 1 0 8-bit asynchronous memory (on CE1 space)
1 0 1 1 16-bit asynchronous memory (on CE1 space)
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Standard serial boot via McBSP0 (16-bit data)
1 1 1 1 Standard serial boot via McBSP0 (8-bit data)
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