TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
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device emulation registers (continued)
The PROTSTART and PROTRANGE registers set the memory address range for which CPU “write” followed
by “read” operations are protected (operations occur in sequence rather then in their natural pipeline order). This
is necessary protection for certain peripheral operations.
Example: The following lines of code perform a write to register 1 (REG1) location and then the next
instruction performs a read from Register 2 (REG2) location. On the processor memory bus,
with block protection disabled, the read operation will be issued before the write as shown:
MOV @REG1,AL ––––– +
TBIT @REG2,#BIT_X ––––– |––––> Read
+––––> Write
If block protection is enabled, then the read is stalled until the write occurs as shown:
MOV @REG1,AL ––––– +
TBIT @REG2,#BIT_X ––– + |
| +––––> Write
+––––––> Read
NOTE: The C28x CPU automatically protects writes followed by reads to the same memory
address. The protection mechanism described above is for cases where the address
is not the same, but within a given region in memory (as defined by the PROTSTART
and POROTRANGE registers).
Table 10. PROTSTART and PROTRANGE Registers
NAME ADDRESS SIZE TYPE RESET DECSRIPTION
PROTSTART 0x0000 0884 16 R/W 0x0100
†
The PROTSTART register sets the starting address relative to the 16
most significant bits of the processors lower 22-bit address reach.
Hence, the smallest resolution is 64 words.
PROTRANGE 0x0000 0885 16 R/W 0x00FF
†
The PROTRANGE register sets the block size (from the starting
address), starting with 64 words and incrementing by binary
multiples (64, 128, 256, 512, 1K, 2K, 4K, 8K, 16K, ...., 2M).
†
The default values of these registers on reset are selected to cover the Peripheral Frame 1, Peripheral Frame 2, and XINTF Zone 1 areas of the
memory map (address range 0x0000 4000 to 0x0000 8000).
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