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TMS320F2812PGFS

Part # TMS320F2812PGFS
Description MIXED-SIGNAL 28X DSPS EXTENDED TEMP
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B APRIL 2001 REVISED SEPTEMBER 2001
22
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
register map (continued)
Table 4. Peripheral Frame 0 Registers
NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE
CPU Emulation Register Space
0x0000 0800
0x0000 087F
128 EALLOW protected
Device Emulation Registers
0x0000 0880
0x0000 09FF
384 EALLOW protected
reserved
0x0000 0A00
0x0000 0B00
128
FLASH Registers
0x0000 0A80
0x0000 0ADF
96
EALLOW protected
CSM Protected
Code Security Module Registers
0x0000 0AE0
0x0000 0AEF
16 EALLOW protected
reserved
0x0000 0AF0
0x0000 0B1F
48
XINTF Registers
0x0000 0B20
0x0000 0B3F
32 Not EALLOW protected
reserved
0x0000 0B40
0x0000 0BFF
192
CPU-TIMER0/1/2 Registers
0x0000 0C00
0x0000 0C3F
64 Not EALLOW protected
reserved
0x0000 0C40
0x0000 0CDF
160
PIE Registers
0x0000 0CE0
0x0000 0CFF
32 Not EALLOW protected
PIE Vector Table
0x0000 0D00
0x0000 0DFF
256 EALLOW protected
reserved
0x0000 0E00
0x0000 0FFF
512
If registers are EALLOW protected, then writes cannot be performed until the user executes the EALLOW instruction. The EDIS instruction
disables writes. This prevents stray code or pointers from corrupting register contents.
The Flash Registers are also protected by the Code Security Module (CSM).
Table 5. Peripheral Frame 1 Registers
§
NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE
eCAN Registers
0x0000 6000
0x0000 61FF
512 User Accessible
reserved
0x0000 6200
0x0000 6FFF
3584
§
Peripheral Frame 1 allows 16-bit and 32-bit accesses. All 32-bit accesses are aligned to even address boundaries.
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B APRIL 2001 REVISED SEPTEMBER 2001
23
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
register map (continued)
Table 6. Peripheral Frame 2 Registers
NAME ADDRESS RANGE SIZE (x16) ACCESS TYPE
reserved
0x0000 7000
0x0000 700F
16
System Control Registers
0x0000 7010
0x0000 702F
32 EALLOW Protected
reserved
0x0000 7030
0x0000 703F
16
SPI-A Registers
0x0000 7040
0x0000 704F
16 Not EALLOW Protected
SCI-A Registers
0x0000 7050
0x0000 705F
16 Not EALLOW Protected
reserved
0x0000 7060
0x0000 706F
16
External Interrupt Registers
0x0000 7070
0x0000 707F
16 Not EALLOW Protected
reserved
0x0000 7080
0x0000 70BF
64
GPIO Mux Registers
0x0000 70C0
0x0000 70DF
32 EALLOW Protected
GPIO Data Registers
0x0000 70E0
0x0000 70FF
32 Not EALLOW Protected
ADC Registers
0x0000 7100
0x0000 711F
32 Not EALLOW Protected
reserved
0x0000 7120
0x0000 73FF
736
EV-A Registers
0x0000 7400
0x0000 743F
64 Not EALLOW Protected
reserved
0x0000 7440
0x0000 74FF
192
EV-B Registers
0x0000 7500
0x0000 753F
64 Not EALLOW Protected
reserved
0x0000 7540
0x0000 774F
528
SCI Registers
0x0000 7750
0x0000 775F
16 Not EALLOW Protected
reserved
0x0000 7760
0x0000 77FF
160
McBSP Registers
0x0000 7800
0x0000 783F
64 Not EALLOW Protected
reserved
0x0000 7840
0x0000 7FFF
1984
Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written).
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B APRIL 2001 REVISED SEPTEMBER 2001
24
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
device emulation registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical device
signals. The registers are defined in Table 7.
Table 7. Device Emulation Registers
NAME ADDRESS RANGE SIZE (x16) DESCRIPTION
DEVICECNF
0x0000 0880
0x0000 0881
2 Device Configuration Register
DEVICEID
0x0000 0882
0x0000 0883
2 Device ID Register
PROTSTART 0x0000 0884 1 Block Protection Start Address Register
PROTRANGE 0x0000 0885 1 Block Protection Range Address Register
reserved
0x0000 0886
0x0000 09FF
378
Table 8. DEVICECNF Register Bit Definitions
BITS NAME TYPE RESET DECSRIPTION
1:0 reserved R/W 1,1 For Test Only
2 reserved R =0 0
3 VMAPS R 0/1 VMAP Configure Status. This indicates the status of VMAP.
4 reserved R = 0 0
5 XRS R 0/1 Reset Input Signal Status. This is connected directly to the XRS input pin.
6 reserved R = 1 1
7 reserved R/W 0
14:8 reserved R = 0 0:0
15 reserved R/W 0 For Test Only
16 reserved R = 1 1
17 reserved R = 1 1
18 reserved R = 1 1
19 ENPROT R/W 1 Enable Write-Read Protection Mode Bit. This bit, when set to 1, will enable
write-read protection as specified by the PROTSTART and PROTRANGE
registers. This bit, when set to 0, disables this protection mode.
31:20 spares R = 0 0
Table 9. DEVICEID Register Bit Definitions
BITS NAME TYPE RESET DECSRIPTION
15:0 PARTID R Dependent on
device
These 16 bits specify the part number of the device as follows:
0x0001: F2810 device
0x0002: F2812 device
31:16 REVID R 0x0001
(for first silicon)
These 16 bits specify the silicon revision number for the particular
part. This number always starts with 0x0001 on the first revision of the
silicon and is incremented on any subsequent revisions.
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