TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

peripheral interrupt expansion (PIE) block

The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block

can support up to 96 peripheral interrupts. On the F2810/F2812, 45 of the possible 96 interrupts are used by

peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into one of 12 CPU interrupt

lines (INT1

to INT12). Each of the 96 interrupts is, supported by its own vector stored in a dedicated RAM block

that can be overwritten by the user. The vector is, automatically fetched by the CPU on servicing the interrupt.

It takes 9 CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly

respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual

interrupt can be enabled/disabled within the PIE block.

external interrupts (XINT1, 2, 13, XNMI)

The F2810 and F2812 support three masked external interrupts (XINT1, 2, 13). XINT13 is combined with one

non-masked external interrupt (XNMI). The combined signal name is XNMI_XINT13. Each of the interrupts can

be selected for negative or positive edge triggering and can also be enabled/disabled (including the XNMI). The

masked interrupts also contain a 16-bit free running up counter, which is reset to zero when a valid interrupt edge

is detected. This counter can be used to accurately time stamp the interrupt.

oscillator and PLL

The F2810 and F2812 can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator

circuit. A PLL is provided supporting up to 10-input clock-scaling ratios. The PLL ratios can be changed

on-the-fly in software, enabling the user to scale back on operating frequency if lower power operation is

desired. The PLL block can be set in bypass mode.

watchdog

The F2810 and F2812 support a watchdog timer. The user software must regularly reset the watchdog counter

within a certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog can

be disabled if necessary.

peripheral clocking

The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption when a

peripheral is not in use. Additionally, the system clock to the serial ports and the event managers, CAP and QEP

blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to be decoupled from

increasing CPU clock speeds.

low-power modes

The F2810 and F2812 devices are full static CMOS devices. Three low-power modes are provided:

IDLE: Place CPU into low-power mode. Peripheral clocks may be turned off selectively and only

those peripherals that need to function during IDLE are left operating. An enabled interrupt

from an active peripheral will wake the processor from IDLE mode.

STANDBY: Turn off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional.

An external interrupt event will wake the processor and the peripherals. Execution begins on

the next valid cycle after detection of the interrupt event.

HALT: Turn off oscillator. This mode basically shuts down the device and places it in the lowest

possible power consumption mode. Only a reset or XNMI will wake the device from this mode.

T PREVIEW

TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

peripheral frames 0, 1, 2 (PFn)

The F2810 and F2812 segregate peripherals into three sections. The mapping of peripherals is as follows:

PF0: XINTF: External Interface Configuration Registers

PIE: PIE Interrupt Enable and Control Registers Plus PIE Vector Table

Flash: Flash Control, Programming, Erase, Verify Registers

Timers: CPU-Timers 0, 1, 2 Registers

CSM: Code Security Module KEY Registers

PF1: eCAN: eCAN Mailbox and Control Registers

PF2: SYS: System Control Registers

GPIO: GPIO Mux Configuration and Control Registers

EV: Event Manager (EVA/EVB) Control Registers

McBSP: McBSP Control and TX/RX Registers

SCI: Serial Communications Interface (SCI) Control and RX/TX Registers

SPI: Serial Peripheral Interface (SPI) Control and RX/TX Registers

ADC: 12-Bit ADC Registers

general-purpose input/output (GPIO) multiplexer

Most of the peripheral signals are multiplexed with general-purpose I/O (GPIO) signals. This enables the user

to use a pin as GPIO if the peripheral signal or function is not used. On reset, all GPIO pins are configured as

inputs. The user can then individually program each pin for GPIO mode or Peripheral Signal mode. For specific

inputs, the user can also select the number of input qualification cycles. This is to filter unwanted noise glitches.

32-bit CPU-Timers (0, 1, 2)

CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The

timers have a 32-bit count down register, which generates an interrupt when the counter reaches zero. The

counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter

reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timers 1 and 2 are reserved for

Real-Time OS (RTOS) applications. CPU-Timer 2 is connected to INT14 of the CPU. CPU-Timer 1 can be

connected to INT13 of the CPU. CPU-Timer 0 is for general use and is connected to the PIE block.

motor control peripherals

The F2810 and F2812 support the following peripherals which, are used for controlling motors:

EV: The event manager module includes general-purpose timers, full-compare/PWM units,

capture inputs (CAP) and quadrature-encoder pulse (QEP) circuits. Two such event

managers are provided which enable two three-phase motors to be driven or four two-phase

motors. The event managers on the F2810 and F2812 are compatible to the event managers

on the 240x devices (with some minor enhancements).

ADC: The ADC block is a 12-bit converter, single ended, 16-channels. It will contain two

sample-and-hold units for simultaneous sampling.

T PREVIEW

TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

serial port peripherals

The F2810 and F2812 support the following serial communication peripherals:

eCAN: This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time stamping

of messages, and is CAN 2.0B-compliant.

McBSP: This is the multichannel buffered serial port that is used to connect to E1/T1 lines,

phone-quality codecs for modem applications or high-quality stereo-quality Audio DAC

devices. The McBSP receive and transmit registers are supported by a 16-level FIFO. This

significantly reduces the overhead for servicing this peripheral.

SPI: The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of

programmed length (one to sixteen bits) to be shifted into and out of the device at a

programmable bit-transfer rate. Normally, the SPI is used for communications between the

DSP controller and external peripherals or another processor. Typical applications include

external I/O or peripheral expansion through devices such as shift registers, display drivers,

and ADCs. Multi-device communications are supported by the master/slave operation of the

SPI. On the F2810 and the F2812, the port supports a 16-level, receive and transmit FIFO

for reducing servicing overhead.

SCI: The serial communications interface is a two-wire asynchronous serial port, commonly

known as UART. On the F2810 and the F2812, the port supports a 16-level, receive and

transmit FIFO for reducing servicing overhead.

The F2810 device contains three peripheral register spaces. The spaces are categorized as follows:

D Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus.

See Table 4.

D Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus.

See Table 5.

D Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus.

See Table 6.

T PREVIEW

Part #	TMS320F2812PGFS
Description	MIXED-SIGNAL 28X DSPS EXTENDED TEMP
Category	IC
Availability	Out of Stock
Qty	0

TMS320F2812PGFS

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Technical Document