TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

description

The TMS320F2810 and TMS320F2812 devices, members of the TMS320C28x DSP generation, are highly

integrated, high-performance solutions for demanding control applications. The functional blocks and the

memory maps are described in subsequent paragraphs.

C28x CPU

The C28x DSP generation is the newest member of the TMS320C2000 DSP platform. The C28x is source

code compatible to the 24x/240x DSP devices, hence existing 240x users can leverage their significant software

investment. Additionally, the C28x is a very efficient C/C++ engine, hence enabling users to develop not only

their system control software in a high-level language, but also enables math algorithms to be developed using

C/C++. The C28x is as efficient in DSP math tasks as it is in system control tasks that typically are handled by

microcontroller devices. This efficiency removes the need for a second processor in many systems. The 32 x

32-bit MAC capabilities of the C28x and its 64-bit processing capabilities, enable the C28x to efficiently handle

higher numerical resolution problems that would otherwise demand a more expensive floating-point processor

solution. Add to this the fast interrupt response with automatic context save of critical registers, resulting in a

device that is capable of servicing many asynchronous events with minimal latency. The C28x has an

8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables the C28x to execute

at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware

minimizes the latency for conditional discontinuities. Special store conditional operations further improve

performance.

memory bus (Harvard bus architecture)

As with many DSP type devices, multiple busses are used to move data between the memories and peripherals

and the CPU. The C28x memory bus architecture contains a program read bus, data read bus and data write

bus. The program read bus consists of 22 address lines and 32 data lines. The data read and write busses

consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single cycle 32-bit

operations. The multiple bus architecture, commonly termed “Harvard Bus”, enables the C28x to fetch an

instruction, read a data value and write a data value in a single cycle. All peripherals and memories attached

to the memory bus will prioritize memory accesses. Generally, the priority of Memory Bus accesses can be

summarized as follows:

Highest: Data Writes

†

Program Writes

†

Data Reads

Program Reads

‡

Lowest: Fetches

‡

peripheral bus

To enable migration of peripherals between various Texas Instruments (TI) DSP family of devices, the F2810

and F2812 adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes

the various busses that make up the processor “Memory Bus” into a single bus consisting of 16 address lines

and 16 or 32 data lines and associated control signals. There are two versions of the peripheral bus supported

on the F2810 and F2812. One version only supports 16-bit accesses (called peripheral frame 2) and this retains

compatibility with C240x compatible peripherals. The other version supports both 16- and 32-bit accesses

(called peripheral frame 1) and is used to connect peripherals requiring higher throughput.

T PREVIEW

TMS320C28x, C28x, and TMS320C2000 are trademarks of Texas Instruments.

†

Simultaneous Data and Program writes cannot occur on the Memory Bus.

‡

Simultaneous Program Reads and Fetches cannot occur on the Memory Bus.

TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

real-time JTAG and analysis

The C28x implements the standard IEEE 1149.1 JTAG interface. Additionally, the C28x supports real-time mode

of operation whereby the contents of memory, peripheral and register locations can be modified while the

processor is running and executing code and servicing interrupts. The user can also single step through

non-time critical code while enabling time-critical interrupts to be serviced without interference. The C28x

implements the real-time mode in hardware within the CPU. This is a unique feature to the C28x, no software

monitor is required. Additionally, special analysis hardware is provided which allows the user to set hardware

breakpoint or data/address watch-points and generate various user selectable break events when a match

occurs.

external interface (XINTF) (F2812 only)

This asynchronous interface consists of 19 address lines, 16 data lines, and four chip-select lines. The

chip-select lines are mapped to five external zones, Zone 0, 1, 2, 6, and 7. Zones 6 and 7 share a single

chip-select. Each of the five zones can be programmed with different number of wait states, strobe signal setup

and hold timing and each zone can be programmed for extending wait states externally or not. The

programmable wait-state, chip-select and programmable strobe timing enables glueless interface to external

memories and peripherals.

flash

The F2812 contains 128K x16 of embedded Flash memory and 2K x16 of OTP memory. The Flash memory

is segregated into eight 4K x16 sized sectors, and six 16K x16 sized sectors. The user can individually erase,

program and validate a sector while leaving other sectors untouched. Special memory pipelining is provided

to enable the Flash module to achieve higher performance. The Flash/OTP is mapped to both program and data

space hence can be used to execute code or store data information.

The F2810 has 64K x 16 of embedded Flash and 2K x 16 of OTP memory.

M0, M1 SARAMs

All C28x devices will contain these two blocks of single access memory, each 1Kx16 in size. The stack pointer

points to the beginning of block M1 on reset. The M0 block overlaps the 240x device B0, B1, B2 RAM blocks

and hence the mapping of data variables on the 240x devices can remain at the same physical address on C28x

devices. The M0 and M1 blocks, like all other memory blocks on C28x devices, are mapped to both program

and data space. Hence, the user can use M0 and M1 to execute code or for data variables. The partitioning is

performed within the linker. The C28x device presents a unified memory map to the programmer. This makes

for easier programming in high-level languages.

L0, L1, H0 SARAMs

The F2810 and the F2812 will contain an additional 16K x 16 of single-access RAM, divided into 3 blocks

(4K + 4K + 8K). Each block can be independently accessed hence minimizing pipeline stalls. Each block is

mapped to both program and data space.

boot ROM

The Boot ROM is factory programmed with boot loading software. Boot-mode signals are provided to tell the

boot loader software, programmed into the Boot ROM, what boot mode to use on power up. The user can select

to boot normally or to download new software from an external connection or to select boot software that is

programmed in the internal Flash. The Boot ROM will also contain standard tables, such as SIN/COS

waveforms, for use in math related algorithms.

T PREVIEW

TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

security

The F2810 and F2812 support high levels of security to protect the user firmware from being reversed

engineered. The security features a 128-bit password, which the user programs into the Flash. One code

security module (CSM) is used to protect the Flash/OTP and the L0/L1 SARAM blocks. The security feature

prevents unauthorized users from examining the memory contents via the JTAG port, executing code from

external memory or trying to boot-load some undesirable software that would export the secure memory

contents. To enable access to the secure blocks, the user must write the correct 128-bit ”KEY” value, which

matches the value stored in the password locations within the Flash.

Code Security Module Disclaimer

The Code Security Module (“CSM”) included on this device was designed to password

protect the data stored in the associated memory (either ROM or Flash) and is warranted

by Texas Instruments (TI), in accordance with its standard terms and conditions, to

conform to TI’s published specifications for the warranty period applicable for this device.

TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE

COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE

ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS.

MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR

REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE,

INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR

A PARTICULAR PURPOSE.

IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL,

INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING

IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT

TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED

DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF

GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER

ECONOMIC LOSS.

T PREVIEW

Part #	TMS320F2812PGFS
Description	MIXED-SIGNAL 28X DSPS EXTENDED TEMP
Category	IC
Availability	Out of Stock
Qty	0

TMS320F2812PGFS

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