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TMS320F2812PGFS

Part # TMS320F2812PGFS
Description MIXED-SIGNAL 28X DSPS EXTENDED TEMP
Category IC
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TMS320F2812PGFS
TMS320F2812PGFS

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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
pin functions (continued)
Table 2. Signal Descriptions (Continued)
GPIO PERIPHERAL SIGNAL PIN NO. I/O/Z DRIVE PU/PD
†
DESCRIPTION
GPIO OR PERIPHERAL SIGNALS
GPIOA OR EVA SIGNALS
GPIOA0 PWM1 (O) I/O/Z PU GPIO or PWM Output Pin #1
GPIOA1 PWM2 (O) I/O/Z PU GPIO or PWM Output Pin #2
GPIOA2 PWM3 (O) I/O/Z PU GPIO or PWM Output Pin #3
GPIOA3 PWM4 (O) I/O/Z PU GPIO or PWM Output Pin #4
GPIOA4 PWM5 (O) I/O/Z PU GPIO or PWM Output Pin #5
GPIOA5 PWM6 (O) I/O/Z PU GPIO or PWM Output Pin #6
GPIOA6 T1PWM_T1CMP (I) I/O/Z PU GPIO or Timer 1 Output
GPIOA7 T2PWM_T2CMP (I) I/O/Z PU GPIO or Timer 2 Output
GPIOA8 CAP1_QEP1 (I) I/O/Z PU GPIO or Capture Input #1
GPIOA9 CAP2_QEP2 (I) I/O/Z PU GPIO or Capture Input #2
GPIOA10 CAP3_QEPI1 (I) I/O/Z PU GPIO or Capture Input #3
GPIOA11 TDIRA (I) I/O/Z PU GPIO or Timer Direction
GPIOA12 TCLKINA (I) I/O/Z PU GPIO or Timer Clock Input
GPIOA13 C1TRIP (I) I/O/Z PU GPIO or Compare 1 Output Trip
GPIOA14 C2TRIP (I) I/O/Z PU GPIO or Compare 2 Output Trip
GPIOA15 C3TRIP (I) I/O/Z PU GPIO or Compare 3 Output Trip
GPIOB OR EVB SIGNALS
GPIOB0 PWM7 (O) I/O/Z PU GPIO or PWM Output Pin #7
GPIOB1 PWM8 (O) I/O/Z PU GPIO or PWM Output Pin #8
GPIOB2 PWM9 (O) I/O/Z PU GPIO or PWM Output Pin #9
GPIOB3 PWM10 (O) I/O/Z PU GPIO or PWM Output Pin #10
GPIOB4 PWM11 (O) I/O/Z PU GPIO or PWM Output Pin #11
GPIOB5 PWM12 (O) I/O/Z PU GPIO or PWM Output Pin #12
GPIOB6 T3PWM_T3CMP (I) I/O/Z PU GPIO or Timer 3 Output
GPIOB7 T4PWM_T4CMP (I) I/O/Z PU GPIO or Timer 4 Output
GPIOB8 CAP4_QEP3 (I) I/O/Z PU GPIO or Capture Input #4
GPIOB9 CAP5_QEP4 (I) I/O/Z PU GPIO or Capture Input #5
GPIOB10 CAP6_QEPI2 (I) I/O/Z PU GPIO or Capture Input #6
GPIOB11 TDIRB (I) I/O/Z PU GPIO or Timer Direction
GPIOB12 TCLKINB (I) I/O/Z PU GPIO or Timer Clock Input
GPIOB13 C4TRIP (I) I/O/Z PU GPIO or Compare 4 Output Trip
GPIOB14 C5TRIP (I) I/O/Z PU GPIO or Compare 5 Output Trip
GPIOB15 C6TRIP (I) I/O/Z PU GPIO or Compare 6 Output Trip
GPIOD OR EVA SIGNALS
GPIOD0 T1CTRIP_PDPINTA (I) I/O/Z PU Timer 1 Compare Output Trip
GPIOD1 T2CTRIP/EVASOC (I) I/O/Z PU Timer 2 Compare Output Trip or External ADC
Start-of-Conversion EV-A
†
PU = pin has internal pullup; PD = pin has internal pulldown
PR
O
DU
C
T PREVIEW
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
pin functions (continued)
Table 2. Signal Descriptions (Continued)
GPIO PERIPHERAL SIGNAL PIN NO. I/O/Z DRIVE PU/PD
†
DESCRIPTION
GPIOD OR EVB SIGNALS
GPIOD5 T3CTRIP_PDPINTB (I) I/O/Z PU Timer 3 Compare Output Trip
GPIOD6 T4CTRIP/EVBSOC (I) I/O/Z PU Timer 4 Compare Output Trip or External ADC
Start-of-Conversion EV-B
GPIOE OR INTERRUPT SIGNALS
GPIOE0 XINT1_XBIO (I) I/O/Z PU GPIO or XINT1 or XBIO core input
GPIOE1 XINT2_ADCSOC (I) I/O/Z PU GPIO or XINT2 or ADC start of conversion
GPIOE2 XNMI_XINT13 (I) I/O/Z PU GPIO or XNMI or XINT13
GPIOF OR SPI SIGNALS
GPIOF0 SPISIMO (O) I/O/Z PU GPIO or SPI slave in, master out
GPIOF1 SPISOMI (I) I/O/Z PU GPIO or SPI slave out, master in
GPIOF2 SPICLK (I/O) I/O/Z PU GPIO or SPI clock
GPIOF3 SPISTE (I/O) I/O/Z PU GPIO or SPI slave transmit enable
GPIOF OR SCI-A SIGNALS
GPIOF4 SCITXDA (O) I/O/Z PU GPIO or SCI asynchronous serial port TX data
GPIOF5 SCIRXDA (I) I/O/Z PU GPIO or SCI asynchronous serial port RX data
GPIOF OR CAN SIGNALS
GPIOF6 CANTX (O) I/O/Z PU GPIO or eCAN transmit data
GPIOF7 CANRX (I) I/O/Z PU GPIO or eCAN receive data
GPIOF OR MCBSP SIGNALS
GPIOF8 MCLKX (I/O) I/O/Z PU GPIO or transmit clock
GPIOF9 MCLKR (I/O) I/O/Z PU GPIO or receive clock
GPIOF10 MFSX (I/O) I/O/Z PU GPIO or transmit frame synch
GPIOF11 MFSR (I/O) I/O/Z PU GPIO or receive frame synch
GPIOF12 MDX (O) I/O/Z PU GPIO or transmitted serial data
GPIOF13 MDR (I) I/O/Z PU GPIO or received serial data
GPIOG OR XF CPU OUTPUT SIGNAL
GPIOF14 XF(0) I/O/Z PU GPIO or input clock
GPIOG OR SCI-B SIGNALS
GPIOG4 SCITXDB (O) I/O/Z PU GPIO or SCI asynchronous serial port transmit data
GPIOG5 SCIRXDB (I) I/O/Z PU GPIO or SCI asynchronous serial port receive data
†
PU = pin has internal pullup; PD = pin has internal pulldown
PR
O
DU
C
T PREVIEW
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
memory map
Block
Start Address
Low 64K
(24x/240x Equivalent Data Space)
0x0000–0000
M0 Vector – RAM (32 × 32)
(enabled if VMAP = 0)
Data Space Prog Space
M0 SARAM (1K × 16)
M1 SARAM (1K × 16)
Peripheral Frame 0
(2K × 16)
0x0000–0040
0x0000–0400
0x0000–0800
PIE Vector - RAM
(256 × 16)
(enabled if VMAP = 0,
ENPIE = 1)
Reserved
Reserved
Reserved
L0 SARAM (4K × 16, Secure Block)
Peripheral Frame 2
(4K × 16, Protected)
Reserved
Peripheral Frame 1
(4K × 16, Protected)
L1 SARAM (4K × 16, Secure Block)
Reserved
OTP (2K × 16, Secure Block)
FLASH (128K × 16, Secure Block)
128-Bit Password
H0 SARAM (8K × 16)
Reserved
Boot ROM (4K × 16)
(enabled if MP/MC
= 0)
BROM Vector - ROM (32 × 32)
(enabled if VMAP = 1, MP/MC
= 0, ENPIE = 0)
0x0000–0D00
0x0000–1000
0x0000–2000
0x0000–6000
0x0000–7000
0x0000–8000
0x0000–9000
0x0000–A000
0x003D–7800
0x003D–8000
0x003F–0000
0x003F–7FF8
0x003F–8000
0x003F–A000
0x003F–F000
0x003F–FFC0
High 64K
(24x/240x Equivalent
Program Space)
Data Space Prog Space
Reserved
XINTF Zone 0 (8K × 16, XZCS0
)
XINTF Zone 1 (8K × 16, XZCS1) (Protected)
Reserved
XINTF Zone 2 (0.5M × 16, XZCS2
)
XINTF Zone 6 (1M × 16, XZCS6AND7)
Reserved
XINTF Zone 7 (16K × 16, XZCS6AND7)
(enabled if MP/MC
= 1)
XINTF Vector - RAM (32 × 32)
(enabled if VMAP = 1, MP/MC
= 1, ENPIE = 0)
On-Chip Memory External Memory XINTF
Only one of these vector maps—M0 vector, PIE vector, BROM vector, XINTF vector—should be enabled at a time.
LEGEND:
0x0008–0000
0x0000–4000
0x0010–0000
0x0020–0000
0x003F–C000
NOTES: A. Memory blocks are not to scale.
B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Boot ROM and Zone 7 memory maps are active either in on-chip or XINTF zone depending on MP/MC
, not in both.
D. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
cannot access these memory maps in program space.
E. “Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
F. Certain memory ranges are EALLOW protected for spurious writes after configuration.
G. Zone 6 and Zone 7 share the same chip select; hence, these memory blocks have mirrored locations.
Figure 1. F2812 Memory Map
PR
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