TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

GPIO mux (continued)

Input

to Qual

Sampling Window QUALPRD

Output

from Qual

1 1 1 1 1 1 1 1 1 1 10 0 0 0 0 0 0 0 0 0

Figure 22. I/P Qualifier Clock Cycles

Table 62. GPAMUX, GPADIR Register Bit Definitions

GPAMUX BIT PERIPHERAL NAME (BIT = 1)

GPIO NAME

(BIT = 0)

GPADIR BIT TYPE RESET

INPUT

QUAL

EV-A Peripheral

0 PWM1 (O) GPIOA0 0 R/W 0 yes

1 PWM2 (O) GPIOA1 1 R/W 0 yes

2 PWM3 (O) GPIOA2 2 R/W 0 yes

3 PWM4 (O) GPIOA3 3 R/W 0 yes

4 PWM5 (O) GPIOA4 4 R/W 0 yes

5 PWM6 (O) GPIOA5 5 R/W 0 yes

6 T1PWM_T1CMP (0) GPIOA6 6 R/W 0 yes

7 T2PWM_T2CMP (0) GPIOA7 7 R/W 0 yes

8 CAP1_QEP1 (I) GPIOA8 8 R/W 0 yes

9 CAP2_QEP2 (I) GPIOA9 9 R/W 0 yes

10 CAP3_QEPI1 (I) GPIOA10 10 R/W 0 yes

11 TDIRA (I) GPIOA11 11 R/W 0 yes

12 TCLKINA (I) GPIOA12 12 R/W 0 yes

13 C1TRIP (I) GPIOA13 13 R/W 0 yes

14 C2TRIP (I) GPIOA14 14 R/W 0 yes

15 C3TRIP (I) GPIOA15 15 R/W 0 yes

T PREVIEW

TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

GPIO mux (continued)

Table 63. GPAQUAL Register Bit Definitions

BIT NAME TYPE RESET DESCRIPTION

7:0 QUALPRD R/W 0:0 Specifies the qualification sampling period:

0x00 no qualification (just SYNC to SYSCLKOUT)

0x01 QUALPRD = SYSCLKOUT/2

0x02 QUALPRD = SYSCLKOUT/4

0xFF QUALPRD = SYSCLKOUT/510

15:8 reserved R=0 0:0

Notes:

1. GPADIR bit = 0, configures corresponding GPIO pin as an input. GPADIR bit = 1, configures corresponding

GPIO pin as an output.

2. The GPADAT, GPASET, GPACLEAR, GPATOGGLE registers have the same bit to I/O signal mapping as

the GPAMUX and GPADIR registers.

3. The GPADAT register is a R/W register. Reading the register will reflect the current state of the input I/O

signal (after qualification). Writing to the register will set the corresponding state of any I/O signal configured

as an output.

4. The GPASET register is a write only register (reads back 0). Writing a 1 to the corresponding bit of an I/O

signal will cause the I/O signal to go high. Writing a 0 will have no effect.

5. The GPACLEAR register is a write only register (reads back 0). Writing a 1 to the corresponding bit of an

I/O signal will cause the I/O signal to go low. Writing a 0 will have no effect.

6. The GPATOGGLE register is a write only register (reads back 0). Writing a 1 to the corresponding bit of an

I/O signal will cause the I/O signal to toggle. Writing a 0 will have no effect.

T PREVIEW

TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

GPIO mux (continued)

Table 64. GPBMUX, GPBDIR Register Bit Definitions

GPBMUX

BIT

PERIPHERAL NAME (BIT = 1)

GPIO NAME

(BIT = 0)

GPBDIR

BIT

TYPE RESET INPUT QUAL

EV-B Peripheral

0 PWM7 (O) GPIOB0 0 R/W 0 yes

1 PWM8 (O) GPIOB1 1 R/W 0 yes

2 PWM9 (O) GPIOB2 2 R/W 0 yes

3 PWM10 (O) GPIOB3 3 R/W 0 yes

4 PWM11 (O) GPIOB4 4 R/W 0 yes

5 PWM12 (O) GPIOB5 5 R/W 0 yes

6 T3PWM_T3CMP (0) GPIOB6 6 R/W 0 yes

7 T4PWM_T4CMP (0) GPIOB7 7 R/W 0 yes

8 CAP4_QEP3 (I) GPIOB8 8 R/W 0 yes

9 CAP5_QEP4 (I) GPIOB9 9 R/W 0 yes

10 CAP6_QEPI2 (I) GPIOB10 10 R/W 0 yes

11 TDIRB (I) GPIOB11 11 R/W 0 yes

12 TCLKINB (I) GPIOB12 12 R/W 0 yes

13 C4TRIP (I) GPIOB13 13 R/W 0 yes

14 C5TRIP (I) GPIOB14 14 R/W 0 yes

15 C6TRIP (I) GPIOB15 15 R/W 0 yes

Table 65. GPBQUAL Register Bit Definitions

BIT NAME TYPE RESET DESCRIPTION

7:0 QUALPRD R/W 0:0 Specifies the qualification sampling period:

0x00 no qualification (just SYNC to SYSCLKOUT)

0x01 QUALPRD = SYSCLKOUT/2

0x02 QUALPRD = SYSCLKOUT/4

0xFF QUALPRD = SYSCLKOUT/510

15:8 reserved R=0 0:0

T PREVIEW

Part #	TMS320F2812PGFS
Description	MIXED-SIGNAL 28X DSPS EXTENDED TEMP
Category	IC
Availability	Out of Stock
Qty	0

TMS320F2812PGFS

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