TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

serial communications interface (SCI) module

The F2810 and F2812 devices include two serial communications interface (SCI) modules. The SCI modules

support digital communications between the CPU and other asynchronous peripherals that use the standard

non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own

separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex

mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing

errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baud-select register.

Features of the SCI module include:

D Two external pins:

– SCITXD: SCI transmit-output pin

– SCIRXD: SCI receive-input pin

NOTE: Both pins can be used as GPIO if not used for SCI.

D Baud rate programmable to 64K different rates

– Up to 9.3 Mbps at 150-MHz SYSCLKOUT

D Data-word format

– One start bit

– Data-word length programmable from one to eight bits

– Optional even/odd/no parity bit

– One or two stop bits

D Four error-detection flags: parity, overrun, framing, and break detection

D Two wake-up multiprocessor modes: idle-line and address bit

D Half- or full-duplex operation

D Double-buffered receive and transmit functions

D Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with

status flags.

– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and

TX EMPTY flag (transmitter-shift register is empty)

– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag

(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)

D Separate enable bits for transmitter and receiver interrupts (except BRKDT)

D NRZ (non-return-to-zero) format

D Ten SCI module control registers located in the control register frame beginning at address 7050h

NOTE: All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register

data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect.

Enhanced features:

D Auto baud-detect hardware logic

D 16-level transmit/receive FIFO

T PREVIEW

TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

serial communications interface (SCI) module (continued)

The SCI port operation is configured and controlled by the registers listed in Table 57 and Table 58.

Table 57. SCI-A Registers

†

NAME ADDRESS RANGE SIZE (x16) DESCRIPTION

SCICCR 0x0000–7050 1 SCI-A Communications Control Register

SCICTL1 0x0000–7051 1 SCI-A Control Register 1

SCIHBAUD 0x0000–7052 1 SCI-A Baud Register, High Bits

SCILBAUD 0x0000–7053 1 SCI-A Baud Register, Low Bits

SCICTL2 0x0000–7054 1 SCI-A Control Register 2

SCIRXST 0x0000–7055 1 SCI-A Receive Status Register

SCIRXEMU 0x0000–7056 1 SCI-A Receive Emulation Data Buffer Register

SCIRXBUF 0x0000–7057 1 SCI-A Receive Data Buffer Register

SCITXBUF 0x0000–7059 1 SCI-A Transmit Data Buffer Register

SCIFFTX 0x0000–705A 1 SCI-A FIFO Transmit Register

SCIFFRX 0x0000–705B 1 SCI-A FIFO Receive Register

SCIFFCT 0x0000–705C 1 SCI-A FIFO Control Register

SCIPRI 0x0000–705F 1 SCI-A Priority Control Register

†

Shaded registers are new registers for the FIFO mode.

Table 58. SCI-B Registers

†

NAME ADDRESS RANGE SIZE (x16) DESCRIPTION

SCICCR 0x0000–7750 1 SCI-B Communications Control Register

SCICTL1 0x0000–7751 1 SCI-B Control Register 1

SCIHBAUD 0x0000–7752 1 SCI-B Baud Register, High Bits

SCILBAUD 0x0000–7753 1 SCI-B Baud Register, Low Bits

SCICTL2 0x0000–7754 1 SCI-B Control Register 2

SCIRXST 0x0000–7755 1 SCI-B Receive Status Register

SCIRXEMU 0x0000–7756 1 SCI-B Receive Emulation Data Buffer Register

SCIRXBUF 0x0000–7757 1 SCI-B Receive Data Buffer Register

SCITXBUF 0x0000–7759 1 SCI-B Transmit Data Buffer Register

SCIFFTX 0x0000–775A 1 SCI-B FIFO Transmit Register

SCIFFRX 0x0000–775B 1 SCI-B FIFO Receive Register

SCIFFCT 0x0000–775C 1 SCI-B FIFO Control Register

SCIPRI 0x0000–775F 1 SCI-B Priority Control Register

†

Shaded registers are new registers for the FIFO mode.

Note:

The above registers are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit

accesses produce undefined results.

T PREVIEW

TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

serial communications interface (SCI) module (continued)

Figure 19 shows the SCI module block diagram.

TX FIFO _0

LSPCLK

WUT

Frame Format and Mode

Even/Odd Enable

Parity

SCI RX Interrupt select logic

BRKDT

RXRDY

SCIRXST.6

SCICTL1.3

SCICTL2.1

RX/BK INT ENA

SCIRXD

SCIRXST.1

TXENA

SCI TX Interrupt select logic

TX EMPTY

TXRDY

SCICTL2.0

TX INT ENA

SCITXD

RXENA

SCIRXD

RXWAKE

SCICTL1.6

RX ERR INT ENA

TXWAKE

SCITXD

SCICCR.6 SCICCR.5

SCITXBUF.7–0

SCIHBAUD. 15 – 8

Baud Rate

MSbyte

SCILBAUD. 7 – 0

Transmitter–Data

Buffer Register

SCICTL2.6

SCICTL2.7

Baud Rate

LSbyte

RXSHF

TXSHF

SCIRXST.5

TX FIFO _1

–––––

TX FIFO _15

TX FIFO registers

TX FIFO Interrupt

TX Interrupt

Logic

TXINT

SCIFFTX.14

RX FIFO _15

SCIRXBUF.7–0

Receive Data

Buffer register

SCIRXBUF.7–0

–––––

RX FIFO_1

RX FIFO _0

RX FIFO registers

SCICTL1.0

RX Interrupt

Logic

RXINT

RX FIFO Interrupt

SCIFFRX.15

RXFFOVF

RX Error

SCIRXST.7

PEFE OE

RX Error

SCIRXST.4 – 2

To CPU

AutoBaud Detect logic

SCICTL1.1

SCIFFENA

Figure 19. Serial Communications Interface (SCI) Module Block Diagram

T PREVIEW

Part #	TMS320F2812PGFS
Description	MIXED-SIGNAL 28X DSPS EXTENDED TEMP
Category	IC
Availability	Out of Stock
Qty	0

TMS320F2812PGFS

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