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TMS320F2812PGFS

Part # TMS320F2812PGFS
Description MIXED-SIGNAL 28X DSPS EXTENDED TEMP
Category IC
Availability Out of Stock
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1 + $17.62840
TMS320F2812PGFS
TMS320F2812PGFS

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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
76
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
multichannel buffered serial port (McBSP) module (continued)
Figure 18 shows the block diagram of the McBSP module with FIFO, interfaced to the F2810 and F2812 version
of Peripheral Frame 2.
McBSP Receive
Interrupt Select Logic
DX
DR
Expand Logic
DRR1 Receive Buffer
RX FIFO
Interrupt
DRR2 Receive Buffer
RX FIFO Registers
RBR1 RegisterRBR2 Register
McBSP Registers and
Control Logic
CLKX
FSX
CLKR
FSR
16
Compand Logic
DXR2 Transmit Buffer
RSR1
XSR2
XSR1
Peripheral Read Bus
16
16
16
16
16
RSR2
DXR1 Transmit Buffer
16
LSPCLK
MRINT
To CPU
McBSP
RX Interrupt Logic
RX FIFO _15
—
RX FIFO _1
RX FIFO _0
RX FIFO _15
—
RX FIFO _1
RX FIFO _0
McBSP Transmit
Interrupt Select Logic
TX FIFO
Interrupt
TX FIFO Registers
MXINT
To CPU
TX Interrupt Logic
16
16
16
TX FIFO _15
—
TX FIFO _1
TX FIFO _0
TX FIFO _15
—
TX FIFO _1
TX FIFO _0
Peripheral Write Bus
Figure 18. McBSP Module With FIFO
PR
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
77
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
multichannel buffered serial port (McBSP) module (continued)
Table 56 provides a summary of the McBSP registers.
Table 56. McBSP Register Summary
NAME
ADDRESS
0x000 xxh
TYPE
(R/W)
RESET VALUE
(HEX)
DESCRIPTION
DATA REGISTERS, RECEIVE, TRANSMIT
†
– – – 0x0000 McBSP Receive Buffer Register
– – – 0x0000 McBSP Receive Shift Register
– – – 0x0000 McBSP Transmit Shift Register
DRR2 00 R 0x0000
McBSP Data Receive Register 2
– Read First if the word size is greater than 16 bits,
else ignore DRR2
DRR1 01 R 0x0000
McBSP Data Receive Register 1
– Read Second if the word size is greater than 16 bits,
else read DRR1 only
DXR2 02 W 0x0000
McBSP Data Transmit Register 2
– Write First if the word size is greater than 16 bits,
else ignore DXR2
DXR1 03 W 0x0000
McBSP Data Transmit Register 1
– Write Second if the word size is greater than 16 bits,
else write to DXR1 only
McBSP CONTROL REGISTERS
SPCR2 04 R/W 0x0000 McBSP Serial Port Control Register 2
SPCR1 05 R/W 0x0000 McBSP Serial Port Control Register 1
RCR2 06 R/W 0x0000 McBSP Receive Control Register 2
RCR1 07 R/W 0x0000 McBSP Receive Control Register 1
XCR2 08 R/W 0x0000 McBSP Transmit Control Register 2
XCR1 09 R/W 0x0000 McBSP Transmit Control Register 1
SRGR2 0A R/W 0x0000 McBSP Sample Rate Generator Register 2
SRGR1 0B R/W 0x0000 McBSP Sample Rate Generator Register 1
MULTICHANNEL CONTROL REGISTERS
MCR2 0C R/W 0x0000 McBSP Multichannel Register 2
MCR1 0D R/W 0x0000 McBSP Multichannel Register 1
RCERA 0E R/W 0x0000 McBSP Receive Channel Enable Register Partition A
RCERB 0F R/W 0x0000 McBSP Receive Channel Enable Register Partition B
XCERA 10 R/W 0x0000 McBSP Transmit Channel Enable Register Partition A
XCERB 11 R/W 0x0000 McBSP Transmit Channel Enable Register Partition B
PCR1 12 R/W 0x0000 McBSP Pin Control Register
RCERC 13 R/W 0x0000 McBSP Receive Channel Enable Register Partition C
RCERD 14 R/W 0x0000 McBSP Receive Channel Enable Register Partition D
XCERC 15 R/W 0x0000 McBSP Transmit Channel Enable Register Partition C
XCERD 16 R/W 0x0000 McBSP Transmit Channel Enable Register Partition D
†
DRR2/DRR1 and DXR2/DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode.
‡
FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers.
PR
O
DU
C
T PREVIEW
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
78
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
multichannel buffered serial port (McBSP) module (continued)
Table 56. McBSP Register Summary (Continued)
NAME
ADDRESS
0x000 xxh
TYPE
(R/W)
RESET VALUE
(HEX)
DESCRIPTION
MULTICHANNEL CONTROL REGISTERS (CONTINUED)
RCERE 17 R/W 0x0000 McBSP Receive Channel Enable Register Partition E
RCERF 18 R/W 0x0000 McBSP Receive Channel Enable Register Partition F
XCERE 19 R/W 0x0000 McBSP Transmit Channel Enable Register Partition E
XCERF 1A R/W 0x0000 McBSP Transmit Channel Enable Register Partition F
RCERG 1B R/W 0x0000 McBSP Receive Channel Enable Register Partition G
RCERH 1C R/W 0x0000 McBSP Receive Channel Enable Register Partition H
XCERG 1D R/W 0x0000 McBSP Transmit Channel Enable Register Partition G
XCERH 1E R/W 0x0000 McBSP Transmit Channel Enable Register Partition H
FIFO MODE REGISTERS (applicable only in FIFO mode)
FIFO Data Registers
‡
DRR2 00 R 0x0000
McBSP Data Receive Register 2 – Top of receive FIFO
– Read First FIFO pointers will not advance
DRR1 01 R 0x0000
McBSP Data Receive Register 1 – Top of receive FIFO
– Read Second for FIFO pointers to advance
DXR2 02 W 0x0000
McBSP Data Transmit Register 2 – Top of transmit FIFO
– Write First FIFO pointers will not advance
DXR1 03 W 0x0000
McBSP Data Transmit Register 1 – Top of transmit FIFO
– Write Second for FIFO pointers to advance
FIFO Control Registers
MFFTX 20 R/W 0xA000 McBSP Transmit FIFO Register
MFFRX 21 R/W 0x201F McBSP Receive FIFO Register
MFFCT 22 R/W 0x0000 McBSP FIFO Control Register
MFFINT 23 R/W 0x0000 McBSP FIFO Interrupt Register
MFFST 24 R/W 0x0000 McBSP FIFO Status Register
†
DRR2/DRR1 and DXR2/DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode.
‡
FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers.
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