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TMS320F2812PGFS

Part # TMS320F2812PGFS
Description MIXED-SIGNAL 28X DSPS EXTENDED TEMP
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B APRIL 2001 REVISED SEPTEMBER 2001
73
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
enhanced controller area network (eCAN) module (continued)
Mailbox Enable CANME
Mailbox Direction CANMD
Transmission Request Set CANTRS
Transmission Request Reset CANTRR
Transmission Acknowledge CANTA
Abort Acknowledge CANAA
Receive Message Pending CANRMP
Receive Message Lost CANRML
Remote Frame Pending CANRFP
Reserved
Master Control CANMC
Bit-Timing Configuration CANBTC
Error and Status CANES
Transmit Error Counter CANTEC
Receive Error Counter CANREC
Global Interrupt Flag 0 CANGIF0
Global Interrupt Mask CANGIM
Mailbox Interrupt Mask CANMIM
Mailbox Interrupt Level CANMIL
Overwrite Protection Control CANOPC
TX I/O Control CANTIOC
RX I/O Control CANRIOC
Local Network Time CANLNT
Global Interrupt Flag 1 CANGIF1
Time-Out Control CANTOC
Time-Out Status CANTOS
Reserved
eCAN Control and Status Registers
Message Identifier MID
61E8h61E9h
Message Control MCF
Message Data Low MDL
Message Data High MDH
Message Mailbox (16 Bytes)
Control and Status Registers
6000h
603Fh
Local Acceptance Masks (LAM)
(32 × 32-Bit RAM)
6040h
607Fh
6080h
60BFh
60C0h
60FFh
eCAN Memory (512 Bytes)
Message Object Time Stamps (MOTS)
(32 × 32-Bit RAM)
Message Object Time-Out (MOTO)
(32 × 32-Bit RAM)
Mailbox 0
6100h6107h
Mailbox 1
6108h610Fh
Mailbox 2
6110h6117h
Mailbox 3
6118h611Fh
eCAN Memory RAM (512 Bytes)
Mailbox 4
6120h6127h
Mailbox 28
61E0h61E7h
Mailbox 29
61E8h61EFh
Mailbox 30
61F0h61F7h
Mailbox 31
61F8h61FFh
61EAh61EBh
61ECh61EDh
61EEh61EFh
Figure 17. eCAN Memory Map
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B APRIL 2001 REVISED SEPTEMBER 2001
74
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
enhanced controller area network (eCAN) module (continued)
The CAN registers listed in Table 55 are used by the CPU to configure and control the CAN controller and the
message objects.
Table 55. CAN Registers Map
REGISTER NAME ADDRESS DESCRIPTION
CANME 0x00 6000 Mailbox enable
CANMD 0x00 6002 Mailbox direction
CANTRS 0x00 6004 Transmit request set
CANTRR 0x00 6006 Transmit request reset
CANTA 0x00 6008 Transmission acknowledge
CANAA 0x00 600A Abort acknowledge
CANRMP 0x00 600C Receive message pending
CANRML 0x00 600E Receive message lost
CANRFP 0x00 6010 Remote frame pending
Reserved 0x00 6012 Reserved
CANMC 0x00 6014 Master control
CANBTC 0x00 6016 Bit-timing configuration
CANES 0x00 6018 Error and status
CANTEC 0x00 601A Transmit error counter
CANREC 0x00 601C Receive error counter
CANGIF0 0x00 601E Global interrupt flag 0
CANGIM 0x00 6020 Global interrupt mask
CANGIF1 0x00 6022 Global interrupt flag 1
CANMIM 0x00 6024 Mailbox interrupt mask
CANMIL 0x00 6026 Mailbox interrupt level
CANOPC 0x00 6028 Overwrite protection control
CANTIOC 0x00 602A TX I/O control
CANRIOC 0x00 602C RX I/O control
CANLNT 0x00 602E Local network time (Reserved in SCC mode)
CANTOC 0x00 6030 Time-out control (Reserved in SCC mode)
CANTOS 0x00 6032 Time-out status (Reserved in SCC mode)
These registers are mapped to Peripheral Frame 1. This space allows 16-bit and 32-bit accesses.
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B APRIL 2001 REVISED SEPTEMBER 2001
75
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
multichannel buffered serial port (McBSP) module
The McBSP module has the following features:
D Compatible to McBSP in TMS320C54x /TMS320C55x DSP devices
D Full-duplex communication
D Double-buffered data registers which allow a continuous data stream
D Independent framing and clocking for receive and transmit
D External shift clock generation or an internal programmable frequency shift clock
D A wide selection of data sizes including 8-, 12-, 16-, 20-, 24-, or 32-bits
D 8-bit data transfers with LSB or MSB first
D Programmable polarity for both frame synchronization and data clocks
D HIghly programmable internal clock and frame generation
D Support A-bis mode
D Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially connected
A/D and D/A devices
D Works with SPI-compatible devices at 75 Mbps maximum for 150-MHz SYSCLKOUT
D Two 16 x 16-level FIFO for Transmit channel
D Two 16 x 16-level FIFO for Receive channel
The following application interfaces can be supported on the McBSP:
D T1/E1 framers
D MVIP switching-compatible and ST-BUS-compliant devices including:
MVIP framers
H.100 framers
SCSA framers
IOM-2 compliant devices
AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.)
IIS-compliant devices
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TMS320C54x and TMS320C55x are trademarks of Texas Instruments.
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