TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

enhanced analog-to-digital converter (ADC) module

A simplified functional block diagram of the ADC module is shown in Figure 15. The ADC module consists of

a 12-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include:

D 12-bit ADC core with built-in S/H

D Analog input: 0 V to 2.5 V

D Fast conversion time:

– Single conversion time: 200 ns

– Pipelined conversion time: 60 ns

D 16-channel, muxed inputs

D Autosequencing capability provides up to 16 “autoconversions” in a single session. Each conversion can

be programmed to select any 1 of 16 input channels

D Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer

(i.e., two cascaded 8-state sequencers)

D Sixteen result registers (individually addressable) to store conversion values

– The digital value of the input analog voltage is derived by:

Digital Value + 4095

Input Analog Voltage * ADCLO

2.5

D Multiple triggers as sources for the start-of-conversion (SOC) sequence

– S/W – software immediate start

– EVA – Event manager A (multiple event sources within EVA)

– EVB – Event manager B (multiple event sources within EVB)

D Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS

D Sequencer can operate in “start/stop” mode, allowing multiple “time-sequenced triggers” to synchronize

conversions

D EVA and EVB triggers can operate independently in dual-sequencer mode

D Sample-and-hold (S/H) acquisition time window has separate prescale control

D Calibration mode

T PREVIEW

TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

enhanced analog-to-digital converter (ADC) module (continued)

The ADC module in the F2810 and F2812 has been enhanced to provide flexible interface to event managers

A and B. The ADC interface is built around a fast, 12-bit ADC module with a total minimum conversion time of

200 ns (S/H + conversion) per conversion. The ADC module has 16 channels, configurable as two independent

8-channel modules to service event managers A and B. The two independent 8-channel modules can be

cascaded to form a 16-channel module. Although there are multiple input channels and two sequencers, there

is only one converter in the ADC module. Figure 15 shows the block diagram of the F2810 and F2812 ADC

module.

The two 8-channel modules have the capability to autosequence a series of conversions, each module has the

choice of selecting any one of the respective eight channels available through an analog mux. In the cascaded

mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer, once the

conversion is complete, the selected channel value is stored in its respective RESULT register. Autosequencing

allows the system to convert the same channel multiple times, allowing the user to perform oversampling

algorithms. This gives increased resolution over traditional single-sampled conversion results.

Result Registers

EVB

S/W

ADCSOC

EVA

S/W

Sequencer 2

Sequencer 1

SOCSOC

ADC Control Registers

70B7h

70B0h

70AFh

70A8h

Result Reg 15

Result Reg 8

Result Reg 7

Result Reg 1

Result Reg 0

Module

ADC

12-Bit

Analog

MUX

ADCIN00

ADCIN07

ADCIN08

ADCIN15

Low-Power

Modes Block

System

Control Block

High-Speed

Prescaler

HALT HSPCLKADCENCLK

C28x

SYSCLKOUT

S/H

Figure 15. Block Diagram of the F2810 and F2812 ADC Module

T PREVIEW

TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

enhanced analog-to-digital converter (ADC) module (continued)

To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent possible,

traces leading to the ADCIN

pins should not run in close proximity to the digital signal paths. This is to minimize

switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation

techniques must be used to isolate the ADC module power pins (such as V

CCA

, V

REFHI

, and V

SSA

) from the

digital supply.

Notes:

1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the ADC module is

controlled by the high-speed peripheral clock (HSPCLK).

2. The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as follows:

ADCENCLK: On reset, this signal will be low. While reset is active-low (XRS

) the clock to the register will still

function. This is necessary to make sure all registers and modes go into their default reset state. The analog

module will however be in a low-power inactive state. As soon as reset goes high, then the clock to the

registers will be disabled. When the user sets the ADCENCLK signal high, then the clocks to the registers

will be enabled and the analog module will be enabled. There will be a certain time delay (ms range) before

the ADC is stable and can be used.

HALT: This signal only affects the analog module. It does not affect the registers. If low, the ADC module is

powered. If high, the ADC module goes into low-power mode. The HALT mode will stop the clock to the CPU,

which will stop the HSPCLK. Therefore the ADC register logic will be turned off indirectly.

T PREVIEW

Part #	TMS320F2812PGFS
Description	MIXED-SIGNAL 28X DSPS EXTENDED TEMP
Category	IC
Availability	Out of Stock
Qty	0

TMS320F2812PGFS

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Technical Document