TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

event manager modules (EVA, EVB)

The event-manager modules include general-purpose (GP) timers, full-compare/PWM units, capture units, and

quadrature-encoder pulse (QEP) circuits. EVA’s and EVB’s timers, compare units, and capture units function

identically. However, timer/unit names differ for EVA and EVB. Table 51 shows the module and signal names

used. Table 51 shows the features and functionality available for the event-manager modules and highlights

EVA nomenclature.

Event managers A and B have identical peripheral register sets with EVA starting at 7400h and EVB starting

at 7500h. The paragraphs in this section describe the function of GP timers, compare units, capture units, and

QEPs using EVA nomenclature. These paragraphs are applicable to EVB with regard to function—however,

module/signal names would differ.

Table 51. Module and Signal Names for EVA and EVB

EVENT MANAGER MODULES

EVA EVB

EVENT MANAGER MODULES

MODULE SIGNAL MODULE SIGNAL

GP Timers

GP Timer 1

GP Timer 2

T1PWM/T1CMP

T2PWM/T2CMP

GP Timer 3

GP Timer 4

T3PWM/T3CMP

T4PWM/T4CMP

Compare Units

Compare 1

Compare 2

Compare 3

PWM1/2

PWM3/4

PWM5/6

Compare 4

Compare 5

Compare 6

PWM7/8

PWM9/10

PWM11/12

Capture Units

Capture 1

Capture 2

Capture 3

CAP1

CAP2

CAP3

Capture 4

Capture 5

Capture 6

CAP4

CAP5

CAP6

QEP Channels

QEP1

QEP2

QEPI1

QEP1

QEP2

QEP3

QEP4

QEPI2

QEP3

QEP4

External Clock Inputs

Direction

External Clock

TDIRA

TCLKINA

Direction

External Clock

TDIRB

TCLKINB

External Compare Inputs Compare

C1TRIP

C2TRIP

C3TRIP

C4TRIP

C5TRIP

C6TRIP

External Trip Inputs

T1CTRIP_PDPINTA

†

T2CTRIP

/EVASOC

T3CTRIP_PDPINTB

†

T4CTRIP

/EVBSOC

†

In the 24x/240x-compatible mode, the T1CTRIP_PDPINTA

pin functions as PDPINTA and the T3CTRIP_PDPINTB pin functions as PDPINTB.

T PREVIEW

TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

event manager modules (EVA, EVB) (continued)

Table 52. EV-A Registers

†

NAME ADDRESS RANGE

SIZE

(x16)

DESCRIPTION

GPTCONA 0x0000–7400 1 GP Timer Control Register A

T1CNT 0x0000–7401 1 GP Timer 1 Counter Register

T1CMPR 0x0000–7402 1 GP Timer 1 Compare Register

T1PR 0x0000–7403 1 GP Timer 1 Period Register

T1CON 0x0000–7404 1 GP Timer 1 Control Register

T2CNT 0x0000–7405 1 GP Timer 2 Counter Register

T2CMPR 0x0000–7406 1 GP Timer 2 Compare Register

T2PR 0x0000–7407 1 GP Timer 2 Period Register

T2CON 0x0000–7408 1 GP Timer 2 Control Register

EXTCONA

‡

0x0000–7409 1 GP Extension Control Register A

COMCONA 0x0000–7411 1 Compare Control Register A

ACTRA 0x0000–7413 1 Compare Action Control Register A

DBTCONA 0x0000–7415 1 Dead-Band Timer Control Register A

CMPR1 0x0000–7417 1 Compare Register 1

CMPR2 0x0000–7418 1 Compare Register 2

CMPR3 0x0000–7419 1 Compare Register 3

CAPCONA 0x0000–7420 1 Capture Control Register A

CAPFIFOA 0x0000–7422 1 Capture FIFO Status Register A

CAP1FIFO 0x0000–7423 1 Two-Level Deep Capture FIFO Stack 1

CAP2FIFO 0x0000–7424 1 Two-Level Deep Capture FIFO Stack 2

CAP3FIFO 0x0000–7425 1 Two-Level Deep Capture FIFO Stack 3

CAP1FBOT 0x0000–7427 1 Bottom Register Of Capture FIFO Stack 1

CAP2FBOT 0x0000–7428 1 Bottom Register Of Capture FIFO Stack 2

CAP2FBOT 0x0000–7429 1 Bottom Register Of Capture FIFO Stack 3

EVAIMRA 0x0000–742C 1 Interrupt Mask Register A

EVAIMRB 0x0000–742D 1 Interrupt Mask Register B

EVAIMRC 0x0000–742E 1 Interrupt Mask Register C

EVAIFRA 0x0000–742F 1 Interrupt Flag Register A

EVAIFRB 0x0000–7430 1 Interrupt Flag Register B

EVAIFRC 0x0000–7431 1 Interrupt Flag Register C

†

The EV-B register set is identical except the address range is from 0x0000–7500 to 0x0000–753F. The above registers are mapped to Zone 2.

This space allows only 16-bit accesses. 32-bit accesses produce undefined results.

‡

New register compared to 24x/240x

T PREVIEW

TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

event manager modules (EVA, EVB) (continued)

EXTCONA is an added control register to enable and disable the added/modified features. It is required for

compatibility with 24x EV. EXTCONA enables and disables the additions and modifications in features. All

additions and modifications are disabled by default to keep compatibility with 24x EV (see Table 53).

Table 53. EXTCONA Register Bit Definitions

BIT(S) NAME TYPE RESET DESCRIPTION

0 INDCOE R/W 0 Independent Compare Output Enable Mode: This bit, when set to one, allows

compare outputs to be enabled and disabled independently.

Independent Compare Output Enable mode is disabled. Time 1 and 2

compare outputs are enabled and disabled at the same time by

GPTCONA(6). Full Compare 1, 2, and 3 outputs are enabled and disabled

at the same time by COMCONA(9). GPTCONA(12,11,5,4) and

COMCONA(7:5, 2:0) are reserved. EVIFRA(0) enables and disables all

the compare outputs at the same time. EVIMR(0) enables and disables

PDP interrupt and the direct path of PDPINT

signal at the same time.

Independent Compare Output Enable mode is enabled. Compare outputs

are enabled and disabled respectively by GPTCONA(5,4) and

COMCONA(7:5). Compare trips are enabled and disabled respectively

by GPTCONA(12,11) and COMCONA(2:0). GPTCONA(6) and

COMCONA(9) are reserved. EVIFRA[0] is set to one when any trip input

is low and is also enabled. EVIMRA(0) functions only as interrupt enable

and disable.

1 QEPIQUAL R/W 0 QEP/CAP3 Index Qualification Mode: This bit turns on and off QEP index

qualifier.

QEPI/CAP3 qualification mode is off. QEPI/CAP3 is allowed to pass the

qualifier unaffected.

QEPI/CAP3 qualification mode is on. A zero-to-one transition is allowed

to pass the qualifier only when both QEPA and QEPB are high. Otherwise

the output of the qualifier stays low.

2 QEPIE R/W 0 QEP Index Enable: This bit enables and disables the QEPI input. The QEPI input

when enabled can cause Timer 2 to reset:

Disable QEPI. Transitions on QEPI don’t affect Timer 2.

Enable QEPI. Either a zero-to-one transition on QEPI alone (when

EXTCONA[1] = 0), or a zero-to-one transition plus QEPA and QEPB are

both high (when EXTCONA[1] = 1), causes Timer 2 to reset to zero.

3 EVSOCE R/W 0 EV Start-of-Conversion Output Enable. This bit enables and disables the EV ADC

start-of-conversion output. When enabled, a negative (active-low) pulse of

32 x HSPCLK is generated on selected EV ADC start-of-conversion event. This

bit does not affect the EVTOADC signal routed to the ADC module as optional

SOC trigger.

Disable EVSOC output. EVSOC is in Hi-Z state.

Enable EVSOC output.

15:4 reserved R = 0 0:0

T PREVIEW

Part #	TMS320F2812PGFS
Description	MIXED-SIGNAL 28X DSPS EXTENDED TEMP
Category	IC
Availability	Out of Stock
Qty	0

TMS320F2812PGFS

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Technical Document