TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

32-bit CPU-Timers 0/1/2 (continued)

Table 43. CPU-Timers 0, 1, 2 Configuration and Control Registers (Continued)

NAME ADDRESS SIZE (x16) DESCRIPTION

TIMER2TIM 0x0000–0C10 1 CPU-Timer 2, Counter Register

TIMER2TIMH 0x0000–0C11 1 CPU-Timer 2, Counter Register High

TIMER2PRD 0x0000–0C12 1 CPU-Timer 2, Period Register

TIMER2PRDH 0x0000–0C13 1 CPU-Timer 2, Period Register High

TIMER2TCR 0x0000–0C14 1 CPU-Timer 2, Control Register

reserved 0x0000–0C15 1

TIMER2TPR 0x0000–0C16 1 CPU-Timer 2, Prescale Register

TIMER2TPRH 0x0000–0C17 1 CPU-Timer 2, Prescale Register High

reserved 0x0000–0C18

0x0000–0C3F

Table 44. TIMERxTIM Register Bit Definitions

†

BITS NAME R/W RESET DESCRIPTION

15:0 TIM R/W 0xFFFF Timer Counter Registers (TIMH:TIM): The TIM register holds the low 16 bits of the current 32-bit

count of the timer. The TIMH register holds the high 16 bits of the current 32-bit count of the timer.

The TIMH:TIM decrements by one every (TDDRH:TDDR+1) clock cycles, where TDDRH:TDDR

is the timer prescale divide-down value. When the TIMH:TIM decrements to zero, the TIMH:TIM

(TINT

) signal is generated.

†

x = 0, 1, or 2

Table 45. TIMERxTIMH Register Bit Definitions

†

BITS NAME R/W RESET DESCRIPTION

15:0 TIMH R/W 0x0000 See description for TIMERxTIM.

†

x = 0, 1, or 2

Table 46. TIMERxPRD Register Bit Definitions

†

BITS NAME R/W RESET DESCRIPTION

15:0 PRD R/W 0xFFFF Timer Period Registers (PRDH:PRD): The PRD register holds the low 16 bits of the 32-bit period.

The PRDH register holds the high 16 bits of the 32-bit period. When the TIMH:TIM decrements to

zero, the TIMH:TIM register is reloaded with the period value contained in the PRDH:PRD

registers, at the start of the next timer input clock cycle (the output of the prescaler). The

PRDH:PRD contents are also loaded into the TIMH:TIM when you set the timer reload bit (TRB)

in the Timer Control Register (TCR).

†

x = 0, 1, or 2

Table 47. TIMERxPRDH Register Bit Definitions

†

BITS NAME R/W RESET DESCRIPTION

15:0 PRDH R/W 0x0000 See description for TIMERxPRD

†

x = 0, 1, or 2

T PREVIEW

TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

32-bit CPU-Timers 0/1/2 (continued)

Table 48. TIMERxTCR Register Bit Definitions

†

BIT NAME R/W RESET DESCRIPTION

15 TIF R/W=1 0 Timer Interrupt Flag. This flag gets set when the timer decrements to zero. This bit can be

cleared by software writing a 1, but it can only be set by the timer reaching zero. Writing a 1

to this bit will clear it, writing a zero has no effect.

14 TIE R/W 0 Timer Interrupt Enable. If the timer decrements to zero, and this bit is set, the timer will assert

its interrupt request.

13:12 Reserved R 0 Reserved

11 FREE R/W 0

Timer Emulation Modes: These bits are special emulation bits that determine the state of

the timer when a breakpoint is encountered in the high-level language debugger. If the

FREE bit is set to 1, then, upon a software breakpoint, the timer continues to run (that is,

free runs). In this case, SOFT is a don’t care. But if FREE is 0, then SOFT takes effect. In

this case, if SOFT = 0, the timer halts the next time the TIMH:TIM decrements. If the SOFT

bit is 1, then the timer halts when the TIMH:TIM has decremented to zero.

FREE SOFT Timer Emulation Mode

10 SOFT R/W 0

FREE SOFT Timer

Emulation

Mode

0 0 Stop after the next decrement of the TIMH:TIM (hard stop)

0 1 Stop after the TIMH:TIM decrements to 0 (soft stop)

1 0 Free run

1 1 Free run

Note: That in the SOFT STOP mode, the timer will generate an interrupt before

shutting down (since reaching 0 is the interrupt causing condition).

9:6 Reserved R/W 0 Reserved

5 TRB W/R=0 0 Timer Reload bit. When you write a 1 to TRB, the TIMH:TIM is loaded with the value in the

PRDH:PRD, and the prescaler counter (PSCH:PSC) is loaded with the value in the timer

divide-down register (TDDRH:TDDR). The TRB bit is always read as zero.

4 TSS R/W 0 Timer stop status bit. TSS is a 1-bit flag that stops or starts the timer. To stop the timer, set

TSS to 1. To start or restart the timer, set TSS to 0. At reset, TSS is cleared to 0 and the timer

immediately starts.

3:0 Reserved R/W 0 Reserved

†

x = 0, 1, or 2

T PREVIEW

TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

32-bit CPU-Timers 0/1/2 (continued)

Table 49. TIMERxTPR Register Bit Definitions

†

BITS NAME R/W RESET DESCRIPTION

7:0 TDDR R/W 0x00 Timer Divide-Down. Every (TDDRH:TDDR + 1) timer clock source cycles, the timer counter

increase the overall timer count by an integer factor, write this factor minus one to the

TDDRH:TDDR bits. When the prescaler counter (PSCH:PSC) value is 0, one timer clock source

cycle later, the contents of the TDDRH:TDDR reload the PSCH:PSC, and the TIMH:TIM

decrements by one. TDDRH:TDDR also reloads the PSCH:PSC whenever the timer reload bit

(TRB) is set by software.

15:8 PSC R 0x00 Timer Prescale Counter. These bits hold the current prescale count for the timer. For every timer

clock source cycle that the PSCH:PSC value is greater than 0, the PSCH:PSC decrements by one.

One timer clock (output of the timer prescaler) cycle after the PSCH:PSC reaches 0, the

PSCH:PSC is loaded with the contents of the TDDRH:TDDR, and the timer counter register

(TIMH:TIM) decrements by one. The PSCH:PSC is also reloaded whenever the timer reload bit

(TRB) is set by software. The PSCH:PSC can be checked by reading the register, but it cannot be

set directly. It must get its value from the timer divide-down register (TDDRH:TDDR). At reset, the

PSCH:PSC is set to 0.

†

x = 0, 1, or 2

Table 50. TIMERxTPRH Register Bit Definitions

†

BIT NAME R/W RESET DESCRIPTION

7:0 TDDRH R/W 0x00 See description of TIMERxTPR.

15:8 PSCH R 0x00 See description of TIMERxTPR.

†

x = 0, 1, or 2

T PREVIEW

Part #	TMS320F2812PGFS
Description	MIXED-SIGNAL 28X DSPS EXTENDED TEMP
Category	IC
Availability	Out of Stock
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TMS320F2812PGFS

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