TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

watchdog block (continued)

Table 37. WDCNTR Register Bit Definitions

BIT(S) NAME TYPE RESET DESCRIPTION

7:0 WDCNTR R/W 0:0 These bits contain the current value of the WD counter. The 8-bit

counter continually increments at the WDCLK rate. If the counter

overflows, then the watchdog initiates a reset. If the WDKEY register

is written with a valid combination, then the counter is reset to zero.

15:8 reserved R=0 0:0

Table 38. WDKEY Register Bit Definitions

BIT(S) NAME TYPE RESET DESCRIPTION

7:0 WDKEY W/R=0 0:0 Writing 0x55 followed by 0xAA will cause the WDCNTR bits to be

cleared. Writing any other value will cause an immediate watchdog

reset to be generated.

15:8 reserved R=0 0:0

Table 39. WDCR Register Bit Definitions

BIT(S) NAME TYPE RESET DESCRIPTION

2:0 WDPS(2:0) R/W 0:0 These bits configure the watchdog counter clock (WDCLK) rate relative

to OSCCLK/512:

000 WDCLK = OSCCLK/512/1

001 WDCLK = OSCCLK/512/1

010 WDCLK = OSCCLK/512/2

011 WDCLK = OSCCLK/512/4

100 WDCLK = OSCCLK/512/8

101 WDCLK = OSCCLK/512/16

110 WDCLK = OSCCLK/512/32

111 WDCLK = OSCCLK/512/64

5:3 WDCHK(2:0) W/R=0 0:0 The user must ALWAYS write “1,0,1” to these bits whenever a write to

this register is performed. Writing any other value will cause an

immediate reset to the core (if WD enabled).

6 WDDIS R/W 0 Writing a 1 to this bit will disable the watchdog module. Writing a 0 will

enable the module. This bit can only be modified if the WDOVERRIDE

bit in the SCSR2 register is set to 1. On reset, the watchdog module is

enabled.

7 WDFLAG R/W=1 Watchdog reset status flag bit. This bit, if set, indicates a watchdog

reset (WDRST

) generated the reset condition. If 0, then it was an

external device or power-up reset condition. This bit remains latched

until the user writes a 1 to clear the condition. Writes of 0 will be ignored.

15:8 reserved R=0 0:0

T PREVIEW

TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

watchdog block (continued)

When the XRS line is low, the WDFLAG bit is forced low. The WDFLAG bit will only be set if a rising edge on

WDRST

signal is detected (after synch and a 4 cycle delay) and the XRS signal is high. If the XRS signal is low

when WDRST

goes high, then the WDFLAG bit will remain at 0. In a typical application, the WDRST signal will

connect to the XRS

input. Hence to distinguish between a watchdog reset and an external device reset, an

external reset must be longer in duration then the watchdog pulse.

Emulation Considerations

The watchdog module behaves as follows under various debug conditions:

CPU Suspended: When the CPU is suspended, the watchdog clock (WDCLK) is

suspended.

Run-Free Mode: When the CPU is placed in run-free mode, then the watchdog module

resumes operation as normal.

Real-Time Single-Step Mode: When the CPU is in real-time single-step mode, the watchdog clock

(WDCLK) is suspended. The watchdog remains suspended even within

real-time interrupts.

Real-Time Run-Free Mode: When the CPU is in real-time run-free mode, the watchdog operates as

normal.

T PREVIEW

TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

low-power modes block

The low-power modes on the F2810 and F2812 are similar to the 240x devices. Table 40 summarizes the

various modes.

Table 40. F2810 and F2812 Low-Power Modes

MODE IDLES LPM(1:0) OSCCLK CLKIN SYSCLKOUT EXIT

†

Normal low X,X on on on –

IDLE high 0,0 on on on

‡

XRS,

WDINT

Any Enabled Interrupt,

XNMI

STANDBY high 0,1 on

(watchdog still

running)

off off XRS,

WDINT

XINT1,

XNMI,

T1/2/3/4CTRIP

C1/2/3/4/5/6TRIP

SCIRXDA,

SCIRXDB,

CANRX,

Debugger

HALT high 1,X off

(oscillator and

PLL turned

off, watchdog

not functional)

off off XRS,

XNMI,

Debugger

†

The Exit column lists which signals or under what conditions the low power mode will be exited. A low signal, on any of the signals, will exit the

low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise the IDLE mode will

not be exited and the device will go back into the indicated low power mode.

‡

The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the core (SYSCLKOUT) is still

functional while on the 24x/240x the clock is turned off.

On the C28x, the JTAG port can still function even if the core clock (CLKIN) is turned off.

The various low-power modes operate as follows:

IDLE Mode: This mode is, exited by any enabled interrupt or an NMI that is recognized

by the processor. The LPM block performs no tasks during this mode as

long as the LPMCR(LPM) bits are set to 0,0.

HALT Mode: Only the XRS

and XNMI external signals can wake the device from HALT

mode. The XNMI input to the core has an enable/disable bit. Hence, it is

safe to use the XNMI signal for this function.

STANDBY Mode: All other signals (including XNMI) will wake the device from STANDBY

Part #	TMS320F2812PGFS
Description	MIXED-SIGNAL 28X DSPS EXTENDED TEMP
Category	IC
Availability	Out of Stock
Qty	0

TMS320F2812PGFS

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Technical Document