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TMS320F2812PGFS

Part # TMS320F2812PGFS
Description MIXED-SIGNAL 28X DSPS EXTENDED TEMP
Category IC
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Technical Document


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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B APRIL 2001 REVISED SEPTEMBER 2001
46
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
system control (continued)
The PCLKCR1 and PCLKCR2 registers basically enable/disable clocks to the various peripheral modules in
the F2810 and F2812 devices. Table 32 lists the bit descriptions of the PCLKCR1 and PCLKCR2 registers.
Table 32. PCLKCR Register Bit Definitions
BIT(S) NAME TYPE RESET DESCRIPTION
0 EVAENCLK R/W 0 If this bit is set, it enables the high-speed clock (HSPCLK) within the EV-A
peripheral. For low power operation, this bit is set to zero by the user or
by reset.
1 EVBENCLK R/W 0 If this bit is set, it enables the high-speed clock (HSPCLK) within the EV-B
peripheral. For low power operation, this bit is set to zero by the user or
by reset.
2 reserved R=0 0 reserved
3 ADCENCLK R/W 0 If this bit is set, it enables the high-speed clock (HSPCLK) within the ADC
peripheral. For low power operation, this bit is set to zero by the user or
by reset.
7:4 reserved R=0 0:0
8 SPIAENCLK R/W 0 If this bit is set, it enables the low-speed clock (LSPCLK) within the SPI
peripheral. For low power operation, this bit is set to zero by the user or
by reset.
9 reserved R=0 0 reserved
10 SCIAENCLK R/W 0 If this bit is set, it enables the low-speed clock (LSPCLK) within the SCI-A
peripheral. For low power operation, this bit is set to zero by the user or
by reset.
11 SCIBENCLK R/W 0 If this bit is set, it enables the low-speed clock (LSPCLK) within the SCI-B
peripheral. For low power operation, this bit is set to zero by the user or
by reset.
12 MAENCLK R/W 0 If this bit is set, it enables the low-speed clock (LSPCLK) within the
McBSP peripheral. For low power operation, this bit is set to zero by the
user or by reset.
13 reserved R=0 0 reserved
14 HECCAENCLK R/W 0 If this bit is set, it enables the system clock within the CAN peripheral. For
low power operation, this bit is set to zero by the user or by reset.
15 reserved R=0 0 reserved
If a peripheral block is not used, then the clock to that peripheral can be turned off to minimize power consumption.
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B APRIL 2001 REVISED SEPTEMBER 2001
47
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
system control (continued)
The system control and status register contains the watchdog override bit and the watchdog interrupt
enable/disable bit. Table 33 describes the bit functions of the SCSR register.
Table 33. SCSR Register Bit Definitions
BIT(S) NAME TYPE RESET DESCRIPTION
0 WDOVERRIDE R/W=1 1 If this bit is set to 1, the user is allowed to change the state of the Watchdog
disable (WDDIS) bit in the Watchdog Control (WDCR) register (refer to
Watchdog Block section of this data sheet). If the WDOVERRIDE bit is
cleared, by writing a 1 the WDDIS bit cannot be modified by the user.
Writing a 0 will have no effect. If this bit is cleared, then it will remain in this
state until a reset occurs. The current state of this bit is readable by the user.
1 WDENINT R/W 0 If this bit is set to 1, the watchdog reset (WDRST) output signal is disabled
and the watchdog interrupt (WDINT
) output signal is enabled. If this bit is
zero, then the WDRST
output signal is enabled and the WDINT output
signal is disabled. This is the default state on reset (XRS
).
15:2 reserved R=0 0:0
The HISPCP and LOSPCP registers are used to configure the high- and low-speed peripheral clocks,
respectively. See Table 34 for the HISPCP bit definitions and Table 35 for the LOSPCP bit definitions.
Table 34. HISPCP Register Bit Definitions
BIT(S) NAME TYPE RESET DESCRIPTION
2:0 HSPCLK R/W 0,0,1 These bits configure the high-speed peripheral clock (HSPCLK) rate
relative to SYSCLKOUT:
000 HSPCLK = SYSCLKOUT / 1
001 HSPCLK = SYSCLKOUT / 2
010 HSPCLK = SYSCLKOUT / 4
011 HSPCLK = SYSCLKOUT / 6
100 HSPCLK = SYSCLKOUT / 8
101 HSPCLK = SYSCLKOUT / 10
110 HSPCLK = SYSCLKOUT / 12
111 HSPCLK = SYSCLKOUT / 14
HSPCLK = SYSCLKOUT / (HSPCLK x 2)
= SYSCLKOUT if HISPCP value is zero
15:3 reserved R=0 0:0
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B APRIL 2001 REVISED SEPTEMBER 2001
48
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443
system control (continued)
Table 35. LOSPCP Register Bit Definitions
BIT(S) NAME TYPE RESET DESCRIPTION
2:0 LSPCLK R/W 0,1,0 These bits configure the low-speed peripheral clock (LSPCLK) rate
relative to SYSCLKOUT:
000 LSPCLK = SYSCLKOUT / 1
001 LSPCLK = SYSCLKOUT / 2
010 LSPCLK = SYSCLKOUT / 4
011 LSPCLK = SYSCLKOUT / 6
100 LSPCLK = SYSCLKOUT / 8
101 LSPCLK = SYSCLKOUT / 10
110 LSPCLK = SYSCLKOUT / 12
111 LSPCLK = SYSCLKOUT / 14
LSPCLK = SYSCLKOUT / (LSPCLK x 2)
= SYSCLKOUT if LOSPCP value is zero
15:3 reserved R=0 0:0
Note: The HSPCLK is set to SYSCLKOUT/2 and LSPCLK is set to SYSCLKOUT/4 on reset.
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