TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

PIE registers (continued)

Table 23. PIECTRL Register Bit Definitions

BIT(S) NAME TYPE RESET DESCRIPTION

0 ENPIE R/W 0 Enable vector fetching from PIE block. When this bit is set to 1, all vectors are fetched from

the PIE vector table. If this bit is set to 0, the PIE block is disabled and vectors are fetched

as normal. All PIE block registers (PIEACK, PIEIFR, PIEIER) can be accessed even when

the PIE block is disabled.

15:1 PIEVECT R 0 Vector fetch address. Displays the address of the vector that was fetched. The least

significant bit of the address is ignored and only bits 1 to 15 are shown. The vector address

can be used to determine which interrupt generated the fetch.

Table 24. PIEACK Register Bit Definitions

BIT(S) NAME TYPE RESET DESCRIPTION

11:0 PIEACK R/W=1 0 Writing a 1 to the respective interrupt bit enables the PIE block to drive a pulse into the CPU

interrupts input, if an interrupt is pending on any of the group interrupts. Reading this

to Bit 11, which refers to INT12.

Note: Writes of 0 are ignored.

15:12 spares R=0 0

Table 25. PIEIERx Register Bit Definitions

†

BIT(S) NAME TYPE RESET DESCRIPTION

0 INTx.1 R/W 0

1 INTx.2 R/W 0

2 INTx.3 R/W 0

3 INTx.4 R/W 0

These register bits individually enable an interru

t within a grou

They behave very much

4 INTx.5 R/W 0

ese reg

bit

y ena

e an

errup

ithi

n a group.

ave very muc

like the CPU interrupt enable register. Setting a bit to 1 will enable the servicing of the

5 INTx.6 R/W 0

the

CPU

interru t

enable

Setting

bit

will

enable

the

servicing

the

respective interrupt. Setting a bit to 0 will disable the servicing of the bit.

6 INTx.7 R/W 0

7 INTx.8 R/W 0

15:8 spares R=0 0

†

x = 1 to 12. INTx means CPU interrupts INT1 to INT12.

Table 26. PIEIFRx Register Bit Definitions

†

BIT(S) NAME TYPE RESET DESCRIPTION

0 INTx.1 R/W 0

1 INTx.2 R/W 0

2 INTx.3 R/W 0

These register bits indicate if an interrupt is currently active. They behave very much like

th CPU i t t fl i t Wh i t ti ti th ti i t bit i t

3 INTx.4 R/W 0

the CPU interrupt flag register. When an interrupt is active, the respective register bit is set.

The bit is cleared when the interru

t is serviced or by writing a 0 to the register bit This

4 INTx.5 R/W 0

The

bit

cleared

hen

the

interr

ser

iced

y w

riting

the

bit

This

5 INTx.6 R/W 0

can

also

read

determine

which

interru ts

are

active

ending.

Note: The PIEIFR register bit is cleared during the interrupt vector fetch portion of

6 INTx.7 R/W 0

Note: The PIEIFR register bit is cleared during the interrupt vector fetch portion of

the interru

rocessing.

7 INTx.8 R/W 0

the

interrupt

processing

15:8 spares R=0 0

†

x = 1 to 12. INTx means CPU interrupts INT1 to INT12.

T PREVIEW

TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

PIE/CPU interrupt response

Figure 8 shows the behavior of the PIE hardware under various PIEIFR and PIEIER register conditions. There

is one PIEACK bit for every CPU interrupt group (INT1 to INT12) and is referred to as PIEACK(x). There is a

corresponding PIEIFR and PIEIER register for each group and are referred to as the PIEIFRx and PIEIERx

registers. Figure 8 describes the operation of one PIE interrupt. This flow is common to all PIE interrupts.

Start

Stage A

PIEIFRx.y = 1

Stage B

PIEIERx.y = 1

Stage C

PIEACKx = 0

Yes

Wait for S/W

to Clear

PIEACKx Bit = 0

Wait for PIEIERx.y = 1

Wait for any

PIEIFRx.y = 1

Stage D

Interrupt Request Sent to

28x CPU on INTx

Stage E

IFRx Bit Set 1

Interrupts to

CPU

Stage F

IERx Bit = 1

Stage G

INTM Bit = 0

Stage H

CPU Responds

Branches to Vector Address at PIEIFRx.y

IFRx Bit Cleared

Context Save

IER = 0

INTM = 1

PIEIFRx.y Bit Cleared

Stage I

Interrupt Service Routine Responds

Write 1 to PIEACKx Bit to Clear to Enable

Other Interrupts in PIEIFRx Group

Re-enable Interrupts, INTM = 0

Return

Yes

Wait for

IERx = 1

Wait for INTM = 0

End

Vector Branch

Interrupt Service

Routine (ISR)

for PIEIFRx.y

PIE Interrupt

Control

CPU Interrupt

Control

Figure 8. Typical PIE/CPU Interrupt Response–INTx.y

T PREVIEW

TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

external interrupts

Table 27. External Interrupts Registers

NAME ADDRESS RANGE SIZE (x16) DESCRIPTION

XINT1CR 0x0000 7070 1 XINT1 configuration register

XINT2CR 0x0000 7071 1 XINT2 configuration register

reserved 0x0000 7072

0x0000 7076

XNMICR 0x0000 7077 1 XNMI configuration register

XINT1CTR 0x0000 7078 1 XINT1 counter register

XINT2CTR 0x0000 7079 1 XINT2 counter register

reserved 0x0000 707A

0x0000 707E

XNMICTR 0x0000 707F 1 XNMI counter register

Each external interrupt can be enabled/disabled or qualified using positive or negative going edge. The register

bits to control this are described in Table 28.

Table 28. XINT1/2CR Register Bit Definitions

BITS NAME TYPE RESET DESCRIPTION

0 ENABLE R/W 0 0 Interrupt Disabled

1 Interrupt Enabled

1 reserved R = 0 0

2 POLARITY R/W 0 0 Interrupt is selected as negative edge triggered

1 Interrupt is selected as positive edge triggered

15:3 reserved R = 0 0:0

Table 29 shows the bit definitions of the XNMICR register.

Table 29. XNMICR Register Bit Definitions

BITS NAME TYPE RESET DESCRIPTION

0 ENABLE R/W 0 0 NMI Interrupt Disabled

1 NMI Interrupt Enabled

1 SELECT R/W 0 0 Timer 1 Connected To INT13

1 XNMI Connected To INT13

2 POLARITY R/W 0 0 Interrupt is selected as negative edge triggered

1 Interrupt is selected as positive edge triggered

15:3 reserved R = 0 0:0

T PREVIEW

Part #	TMS320F2812PGFS
Description	MIXED-SIGNAL 28X DSPS EXTENDED TEMP
Category	IC
Availability	Out of Stock
Qty	0

TMS320F2812PGFS

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